Product category:
Intellectual Property Cores
News Release from: Lattice Semiconductor UK | Subject: IspLeverCore IP cores
Edited by the Electronicstalk Editorial
Team on 01 June 2005
IP cores are ready to run on latest FPGA
family
Lattice Semiconductor has released a range of key ispLeverCore intellectual property (IP) modules for its recently announced LatticeXP FPGAs.
Lattice Semiconductor has released a range of key ispLeverCore intellectual property (IP) modules for its recently announced LatticeXP FPGAs Easily integrated into the Lattice ispLever design tool suite, and optimised to take full advantage of the LatticeXP architecture, the initial IP cores include Ethernet, PCI, DMA, FCRAM and DDR and target the consumer, computing and communications markets
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Throughout 2005, the LatticeXP IP portfolio will continue to expand with the availability of several additional ispLeverCore modules, complemented by IP cores from Lattice third party partners and by free, industry-standard reference designs.
Lattice ispLeverCore IP modules are designed to the highest coding standards and are extensively tested to meet required functionality and performance.
These cores are ready to use, well documented and fully supported by Lattice field and factory engineers.
"These initial IP cores reflect Lattice's ongoing commitment to bringing the best together for our customers", said Stan Kopec, Lattice Vice President of Corporate Marketing.
"These IP modules, coupled with the unique, nonvolatile architecture of our LatticeXP FPGAs, reduce overall design complexity, allow designers to focus on their unique design concerns and, consequently, accelerate our customers' time to market", Kopec concluded.
Complementing the Lattice ispLeverCore IP cores are free reference designs that support a number of functions.
These reference designs are available now and come with either source code or a netlist: QDR II SDRAM controller; SDR SDRAM controller; I2C bus master controller; 1553 databus encoder/decoder; RGMII to GMII bridge; and POS PHY Level 3 link.
IP evaluation packages are available now on the Lattice website for immediate download at no charge.
Each evaluation package contains a model for functional simulation and an evaluation netlist for fitting purposes and static timing analysis.
These ispLeverCore IP modules are available now: 10/100 Ethernet MAC; 1G Ethernet MAC; PCI; multichannel DMA controller; FCRAM controller; and DDR controller.
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