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Product category: Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeXP
Edited by the Electronicstalk Editorial Team on 12 August 2005

Nonvolatile FPGAs sleep on the job to
save energy

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Lattice Semiconductor has developed a novel power-saving feature that reduces standby power by over a factor of 1000 for its LatticeXP family of nonvolatile FPGAs.

Lattice Semiconductor has developed a novel power-saving feature that reduces standby power by over a factor of 1000 for its LatticeXP family of nonvolatile FPGAs Sleep mode uses the LatticeXP device's unique Flash and SRAM architecture to provide an ultralow standby state that can be entered in nanoseconds and exited in less than 2ms

While in sleep mode, the LatticeXP device draws as little as 120uA of total power supply current.

"The need for reduced power consumption has been largely unmet by mainstream FPGAs", said Stan Kopec, Lattice Vice President of Corporate Marketing.

"The new sleep mode, now available in our LatticeXP FPGAs, allows our customers to achieve the low power operation they require while still enjoying the design flexibility of a mainstream FPGA".

To reduce power consumption, a wide variety of integrated circuit manufacturers have added sleep, or standby, modes to their devices.

Lattice now leads the FPGA industry by incorporating, for the first time, this approach into a mainstream, LUT-based FPGA.

A single pin called "sleepn" controls entry into and exit from sleep mode.

When this pin is held high, the device operates normally.

When driven low, the device moves into sleep mode in less than 100ns.

In sleep mode, the total device standby current is as little as 120uA.

When sleepn is driven high again, the device configuration is automatically restored from the on-chip Flash block and resumes normal operation after a maximum delay of 2ms.

Nonvolatile LatticeXP FPGAs deliver the benefits of instant-on operation, excellent security and a single-chip implementation, and provide cost-effective alternatives to traditional SRAM-based FPGAs and their associated boot memories.

The ispXP technology used in the LatticeXP devices combines SRAM and nonvolatile Flash memory to deliver an FPGA that is both nonvolatile and infinitely reconfigurable.

The SRAM-based memory cells control the operation of the device logic and are loaded from the on-chip Flash memory in less than 1ms at power-up - providing instant-on capability - or on user command.

Unlike SRAM-based FPGAs, the LatticeXP device does not require an external boot memory and so provides a single-chip solution with the associated benefits of reduced board area and simplified system manufacture.

The absence of an external boot device also eliminates the need for an external bit-stream at boot up and the possibility of bitstream snooping, a major security concern with SRAM FPGAs.

Security features prohibit bit-stream readback from the SRAM and Flash sections of the devices to further enhance security.

The LatticeXP FPGA family includes five logic capacities: 3, 6, 10, 15 and 20K LUTs.

The 3, 6, and 10K versions are sampling now.

For each capacity, there are two power supply versions: a C-version that supports 3.3, 2.5 and 1.8V operation, and an E-version that supports 1.2V operation.

The sleep mode is available on all C-versions of the device.

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