Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeXP FPGA
Edited by the Electronicstalk Editorial
Team on 14 November 2005
Design services company chooses
LatticeXP FPGA
Lattice Semiconductor has announced that design services firm Oztek has chosen the LatticeXP FPGA for use in several distinct designs.
Lattice Semiconductor has announced that design services firm Oztek has chosen the LatticeXP FPGA for use in several distinct designs "In one case, we designed a power supply for a high-end instrumentation product", said Dave Zendzian, Oztek co-founder and Vice President of Engineering
This article was originally published on Electronicstalk on 1 Jun 2005 at 8.00am (UK)
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"The power supply is comprised of 16 dual output cards in the motherboard, as well as a microprocessor".
"The design originally called for a CPLD, but the amount of logic in the design was more than the CPLD could comfortably accommodate".
"We chose to substitute a LatticeXP FPGA for the CPLD".
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"There are multiple interfaces in the design, including SPI, serial and A/D convertors".
"The LatticeXP device provides a seamless bridge to these interfaces, and easily handles the amount of logic required", Zendzian continued".
"We faced a similar challenge in the design of a power control system for a robotics application", said Zendzian".
"Again, 'logic creep' made the use of a CPLD impractical".
"Because the LatticeXP device is nonvolatile, it was very easy to migrate the design because the LatticeXP FPGA requires no external boot PROM".
"While the design consumed virtually 100% of the CPLD, just 20% of the LatticeXP resources were needed".
"And the cost of the Lattice FPGA was about half that of the CPLD", Zendzian noted".
"Our most recent design, a handheld, battery-powered instrumentation device, takes full advantage of the LatticeXP FPGA features", said Zendzian.
"The design requires a lot of logic, dual port RAM and PLL features".
"The LatticeXP device is used to implement a UART, a DSP bus interface and instrument control functions".
"Because the device is portable and battery-powered, size and power consumption are critical considerations".
"The LatticeXP FPGA is nonvolatile, so it can be shut down to save power using the Sleep mode feature, and boot up takes only milliseconds".
"Nonvolatility means a single-chip solution, saving space as well as reducing our design cycle".
"We've also been very pleased with the local Lattice support; Lattice people have been a genuine partner in these designs, and their expertise has been invaluable", Zendzian concluded.
"The LatticeXP device is the only nonvolatile FPGA that exploits the full potential of Flash plus SRAM technology", said Stan Kopec, Lattice Vice President of Marketing".
"That combination makes our LatticeXP devices the only full-featured nonvolatile FPGAs that are infinitely reconfigurable and that can be transparently upgraded in the field".
"At the same time, our customers receive the traditional benefits of nonvolatility, including high security and a single-chip, space saving solution", Kopec concluded.
Nonvolatile LatticeXP FPGAs deliver the benefits of instant-on operation, excellent security and a single-chip implementation, and provide cost-effective alternatives to traditional SRAM-based FPGAs and their associated boot memories.
The ispXP technology used in the LatticeXP devices combines SRAM and nonvolatile Flash memory to deliver an FPGA that is both nonvolatile and infinitely reconfigurable.
The SRAM-based memory cells control the operation of the device logic and are loaded from the on-chip Flash memory in less than 1ms at power-up - providing instant-on capability - or on user command.
Unlike SRAM-based FPGAs, the LatticeXP device does not require an external boot memory and so provides a single-chip solution with the associated benefits of reduced board area and simplified system manufacture.
The absence of an external boot device also eliminates the need for an external bit-stream at boot up and the possibility of bitstream snooping, a major security concern with SRAM FPGAs.
Security features prohibit bit-stream readback from the SRAM and Flash sections of the devices to further enhance security.
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