Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: IspClock5600A
Edited by the Electronicstalk Editorial
Team on 06 December 2005
In-system-programmable clocks add more
features
The ispClock5600A is the second-generation family of enhanced zero-delay clock generators from Lattice Semiconductor.
Lattice Semiconductor has announced its new ispClock second generation family of enhanced zero-delay clock generators, the ispClock5600A devices, along with the availability of the first device, the ispClock5620A The programmable, E2CMOS-based ispClock5620 devices can generate up to 20 clock outputs, each with independently programmable output skew, I/O standard and frequency selection
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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The nonvolatile, in-system-programmable ispClock5600A devices are pin compatible with Lattice's first generation ispClock5600 devices, but provide a number of significant additional features and parametric enhancements.
Heading the list of significant enhancements, the maximum VCO operating frequency of the ispClock5600A devices has been increased to 800MHz.
This supports the generation of popular clock frequencies such as 33.33, 100, 133.33 and 50MHz simultaneously from a single master frequency.
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The input clock frequency range has been extended (5 to 400MHz) to enable support at 8.192MHz, a popular telecomms clock frequency.
Additionally, the device's universal fanout buffer is able to source clocks to DDRII and QDRII memories (up to 400MHz).
"Our ispClock5600A devices substantially reduce clock network design effort", said Stan Kopec, Lattice Corporate Vice President of Marketing.
"Traditionally, as the performance requirements of the system increased, the effort required to generate and distribute clocks grew exponentially".
"Our programmable ispClock5600A devices provide unprecedented convenience to designers without compromising the system specifications".
"The devices provide faster time to market, reduced board space and improved manufacturability and reliability".
The ispClock5600A devices use seven on-chip counters (input, feedback and five for outputs) to provide fine granularity output frequency generation.
The high-performance universal fan-out buffer has a maximum pin-to-pin skew of 50ps, regardless of bank and frequency, the maximum cycle-cycle (peak-peak) output jitter is less than 70ps, and the period jitter less than 12ps (RMS).
The output skew of each clock net relative to the reference input can be further controlled in delay increments of 156ps (lead or lag) to compensate for differences in circuit board clock network trace length.
In addition, both the reference input and the Universal Fan-out Buffers can support a wide variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, differential HSTL, differential SSTL) at a variety of voltage levels.
The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.
The Lattice Windows-based design software, PAC-Designer Version 4.1, provides comprehensive design support for the ispClock5600A device family.
In addition, utilities such as graphical skew editor, frequency calculator and frequency synthesis support have been enhanced to address a wider range of application issues.
Design configurations can be downloaded quickly into ispClock5600A devices via the PC parallel port.
This version of the PAC-Designer software can be downloaded for free from the Lattice website.
Prices for the first available device, the ispClock5620A, start at $6.80 in high volume (10,000 unit) quantities.
The ispClock5620A, packaged in a 100-pin TQFP, is available immediately in both commercial (0 to +70C) and industrial (-40 to +85C) temperature grades.
PACsystemCLK5620A evaluation kits also are available through authorised Lattice distributors or on the Lattice website for $295.
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