Crossover programmable logic fills the gap

All members of the MachXO "crossover PLD" family are now shipping in volume.

Lattice Semiconductor has announced the production release of the two largest members of its 130nm MachXO family, the MachXO1200 and MachXO2280 devices.

All members of the MachXO "crossover PLD" family are now shipping in volume.

Lattice initially announced the MachXO family in July of this year.

Five months later, Lattice has now released the last of the devices, and all family members are now in volume production.

The MachXO devices are already making their way into production systems in the computing, consumer, industrial and automotive market segments.

"Lattice has always strived to provide its customers with product announcements that strike the proper balance between providing insight into next generation product roadmaps and access to real silicon that designers can take advantage of in the near term".

"Lattice is happy to again meet our customers' needs for a high performance, full-featured PLD family, made available in a timely fashion", said Stan Kopec, Lattice Corporate Vice President of Marketing.

"Our customers are responding enthusiastically to the MachXO device's crossover architecture, and features such as infinite reconfigurability, instant-on operation, flexible I/O standards, sleep mode and TransFR field upgrades".

The MachXO family defines a new class of crossover programmable logic device that supports applications traditionally addressed either by high density CPLDs or low capacity FPGAs.

Through the use of 130nm nonvolatile embedded Flash process technology that efficiently integrates between 256 and 2280 four-input look-up tables (LUTs) for logic implementation, these new devices provide system designers with up to 50% lower cost per logic function, yet deliver a dramatic increase in features.

User I/O counts range from 72 to 271 I/Os, accommodating the diverse needs of users of this PLD density range.

Not content merely to address traditional CPLD applications with its MachXO devices, Lattice has added distributed memory to all family members.

In addition, support for Embedded Block RAM (EBR) and phase-locked loop (PLL) clock circuitry, as well as PCI and LVDS I/O, has been added to the larger family members, providing functionality typically found only in traditional FPGA architectures.

At the same time, the instant on, single-chip and high-speed benefits of previous generations of Lattice CPLDs, such as its popular MACH devices, have been preserved.

Lattice MachXO devices are ideal for a wide array of functions, including bus bridging, interfacing, control logic, clock management, power and reset control, glue logic, memory control and ASIC and FPGA configuration.

The Lattice MachXO devices incorporate best in class innovations such as sleep mode and TransFR technology.

Sleep mode enables up to a 100x reduction in standby power, supporting applications that demand low power.

TransFR (transparent field reconfiguration) technology allows the Flash configuration storage to be programmed transparently while the device continues to operate normally from its SRAM configuration storage.

The new configuration can be downloaded when convenient from the Flash to the SRAM blocks in milliseconds.

TransFR technology allows devices to be updated without disrupting system operation, enabling the flexibility of field logic updates while maintaining "5 nines" (99.999%) or better system availability.

The MachXO1200 and MachXO2280 devices are available now in 100-pin thin quad flat pack (TQFP), 144-pin TQFP, 132-ball chip scale BGA (csBGA), 256-ball fine pitch thin bga (ftBGA) and 324-ball ftBGA (MachXO2280 only) in both commercial (0 to +85C) and industrial (-40 to +100C) temperature grades.

A variety of power supply options are supported through the 1.2V E version and 1.8, 2.5 or 3.3V C version.

In high volumes (250,000 units), the 1200 LUT MachXO1200 device will be priced as low as $3.50, whereas the 2280 LUT MachXO2280 device will be priced as low as $5.00.

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