IP cores are tailored for top-performing FPGAs

Lattice Semiconductor has released an extensive intellectual property (IP) portfolio for its LatticeSC Extreme Performance FPGA family.

Lattice Semiconductor has released an extensive intellectual property (IP) portfolio for its LatticeSC Extreme Performance FPGA family.

The portfolio includes 44 IP cores, including both Lattice-created ispLeverCore blocks and third-party ispLeverCore Connection blocks.

These new IP cores are in addition to the pre-engineered MACO (masked array for cost optimisation) IP blocks available on LatticeSCM FPGAs.

Lattice also has made most of its initial ispLeverCore blocks for the LatticeSC family available with the new IPexpress flow, enabling easy user-controllable configuration of many popular IP cores.

Since the introduction of the LatticeSC device family in February 2006, Lattice has delivered IP cores for customers who need system solutions and faster time to market for communications, connectivity, controllers and DSP applications.

The Lattice ispLeverCore IP portfolio comprises a range of in-demand technologies including PCI, CPRI, OBSAI, Ethernet, DDR2 and encoders/decoders.

Lattice ispLeverCore Connection partners CAST, DCD, Elliptic and Northwest Logic have made additional and significant contributions to the portfolio.

"We've already delivered the highest performance and most robust feature set in the industry for high-end FPGAs".

"Now we and our partners have delivered comprehensive IP support for popular standards, fast integration and high performance in less than four months, which is unprecedented", said Stan Kopec, Lattice Corporate Vice President of Marketing.

"Customers designing with LatticeSC devices can quickly and easily incorporate our ispLeverCore and ispLeverCore Connection IP blocks with our IPexpress flow and our ispLever software design tool suite, enabling fast system solutions and accelerated time to market".

The LatticeSC device family includes several prefabricated and optimised I/O and physical layer circuits to simplify implementation and enhance performance for the most demanding designs.

In particular, the DDR and DDR2 SDRAM controller IP cores work with gearing circuitry on both input and output register blocks residing within the LatticeSC's Purespeed I/O interface in order to ensure timing synchronisation of databuses at the interface.

Dedicated data alignment and DQS circuitry is also included in the Purespeed I/O interface for DDR and DDR2.

The 10Gbit/s Ethernet MAC IP core also benefits from embedded hard logic in the exclusive LatticeSC physical coding sublayer (PCS), including clock tolerance compensation, channel alignment, 8b/10b encoding and word alignment/link synchronisation.

The Lattice ispLeverCore blocks supported by the IPexpress design flow include several versions of conventional PCI including PCI master/target 64bit/66MHz, block Viterbi decoder, DDR 200 SDRAM controller, DDR2 200 SDRAM controller, soft error detection, CPRI, OBSAI and 10Gbit/s Ethernet MAC.

The 10/100/1000 Ethernet MAC and DMA controller are also available with the standard ispLever design flow.

Back to top