Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: IspClock5300S family
Edited by the Electronicstalk Editorial
Team on 21 June 2006
Programmable clocks suit smaller systems
Family of in-system-programmable zero-delay single-ended clock buffer devices adds cost-effective eight- and four-output options.
Lattice Semiconductor has expanded its ispClock5300S family of in-system programmable, zero-delay, single-ended clock buffer devices, with the production release of the new ispClock5308S (eight-output) and the ispClock5304S (four-output) chips These new devices provide lower cost alternatives to the previously announced 12-output ispClock5312S
This article was originally published on Electronicstalk on 1 Nov 2006 at 8.00am (UK)
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All three members of the E2CMOS-based ispClock5300S device family are pin compatible and offer programmable clock skew, termination and interface standard support.
The ispClock5300S devices support four operating configurations, including zero-delay buffer mode, combined zero-delay and non-zero-delay fan-out mode, dual fan-out buffer mode and fan-out buffer mode with output dividers.
"Our ispClock5300S device family is an ideal low cost clock distribution device for any microprocessor-based system", said Stan Kopec, Lattice Corporate Vice President of Marketing.
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"With this family expansion, designers can take advantage of ispClock's programmable skew, termination and JTAG-based boundary scan testing capabilities, even for systems requiring only a handful of clock nets".
The ispClock5300S family allows each pin to be configured for the necessary functions individually, resulting in a simple programmable solution that can be customised to suit the design requirements of each circuit board.
The programmable interface type, skew, termination and slew rate features further reduce the design effort and result in both reduced board space and improved board manufacturability and reliability.
Designers now will be able to standardise on the ispClock5300S family for all their clock distribution needs, rather than using disparate clock distribution devices from different vendors.
Consequently, inventory is more easily managed and costs are further reduced.
The ispClock5300S devices use three, 5bit on-chip output counters to generate up to three clocking frequencies derived from one reference.
Output clock frequencies can range up to 267MHz.
The high-performance universal fan-out buffer has a maximum pin-to-pin skew of 100ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps and the period jitter is less than 12ps (RMS).
The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156ps (lead or lag) to compensate for differences in circuit board clock network trace length.
The Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs.
The input termination and output impedance of each output can be individually tuned to match each trace impedance, which results in clock nets with high signal integrity.
The ispClock5300S devices can integrate multiple types of clock distribution ICs such as zero-delay buffers, fan-out buffers and translators, so designers can easily select the features needed for each individual output pin in their application.
In addition, the reference clock input integrates the necessary termination resistors, simplifying interfaces to popular single-ended as well as differential logic interface standards such as LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, differential HSTL and differential SSTL at a variety of voltage levels.
Traditionally, clock network designs are constrained to maintain equal clock trace lengths to ensure timing integrity using serpentine patterns to accommodate the extra length clock traces.
Because the outputs of the ispClock5300S devices can be skewed precisely in 156ps increments, designers can route clock patterns more conveniently, and can compensate for the clock edge arrival delay by skewing each output at the device.
To meet strict EMI standards, designers have commonly resorted to using spread spectrum clocks, which intentionally introduce jitter to diffuse peak power emissions due to coincident clock edge across multiple devices.
However, the increased jitter in the clock is frequently not desirable.
The fine output skew feature of the ispClock5300S devices enables designers to stagger the clock edge in steps of 156ps, allowing the clocking edge to be spread without introducing jitter, and creating a superior method for EMI emission reduction.
The Lattice PC-based mixed signal software design tool, PAC-Designer Version 4.6, provides comprehensive support for all ispClock5300S devices.
Design configurations can be downloaded quickly via the PC parallel port.
This version of the PAC-Designer software can be downloaded for free from the Lattice website.
Prices for the ispClock5308S and ispClock5304S start at $2.75 and $2.45, respectively, in 10,000-unit quantities.
All three members of the ispClock5300S family, in a pin compatible 48-pin TQFP package, are available immediately in both commercial (0 to +70C) and industrial (-40 to +85C) temperature grades.
PAC-SystemCLK5312S evaluation kits can be used with all three family members and are available through authorised Lattice distributors or on the Lattice website for $295.
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