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News Release from: Lattice Semiconductor UK | Subject: LatticeMico32
Edited by the Electronicstalk Editorial
Team on 20 September 2006
Soft microprocessor is optimised for
Lattice FPGAs
Lattice Semiconductor Corp has announced the immediate availability of the LatticeMico32, a 32bit soft microprocessor optimised for Lattice FPGAs.
Lattice Semiconductor Corp has announced the immediate availability of the LatticeMico32, a 32bit soft microprocessor optimised for Lattice FPGAs Lattice is releasing the HDL code of the microprocessor core and various peripheral components generated by the LatticeMico32 System, along with selected tools, in an open source format that provides visibility, flexibility and portability
This article was originally published on Electronicstalk on 25 Oct 2006 at 8.00am (UK)
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Support allows developers to rapidly implement control systems in a design flow that builds on Lattice's open source embedded solutions approach.
The heart of the product is the LatticeMico32 system development tool suite, which provides a fast and easy way to implement microprocessor designs from platform definition to software development and debug.
This flexible microprocessor will find application in a wide variety of markets including communications, consumer, computing, medical, industrial and automotive.
"The LatticeMico32 microprocessor is a comprehensive, high performance and easy to use 32bit processor solution", said Stan Kopec, Lattice Corporate Vice President of Marketing.
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"The LatticeMico32 open source license is another industry first from Lattice that provides our customers with an extraordinary embedded processor and related development environment at no charge", Kopec concluded.
"The LatticeMico32 is high performance IP that delivers exceptional code size, speed and functionality", said Chris Fanning, Corporate Vice President of Software and IP Solutions.
"The LatticeMico32 System seamlessly interfaces to our easy to use ispLever design flow".
The LatticeMico32 microprocessor uses fewer than 2000 look-up tables (LUTs), which results in a cost of less than $1.00 of FPGA logic in select LatticeECP2 FPGAs in high volume.
The RISC, Harvard-based architecture uses 32bit for data path and instructions and supports optional data and instruction caches, as well as user-defined instructions.
The LatticeMico32 is distinct from other FPGA embedded microprocessors with exclusive features that include: 32 general purpose registers, up to 32 external interrupts and a dual wishbone memory interface.
The LatticeMico32 maintains the high performance required for a breadth of applications, with a maximum clock frequency of over 100MHz (estimated) for LatticeECP2 FPGAs.
To accelerate the development of microprocessor systems, several optional peripheral components may be integrated with the LatticeMico32.
These peripheral components are connected to the microprocessor via a Wishbone bus interface, which is a royalty-free, public domain specification.
The peripheral components include: An asynchronous SRAM controller; an on-chip block memory controller; a 32bit timer; a DMA controller; general purpose IO (GPIO); an I2C master controller; a Serial Peripheral Interface (SPI); and a universal asynchronous receiver transmitter (UART).
The LatticeMico32 system development tools, based on the Eclipse C development tools (CDT) environment, seamlessly integrate with the Lattice ispLever tool suite (version 6.0 SP1 or higher) to enable designers to build microprocessor systems on Lattice FPGAs.
The LatticeMico32 System comprises three tools: the Mico System Builder (MSB), the C/C++ Software Project Environment (SPE) and the Debugger.
The MSB generates platform descriptions and the associated HDL code for hardware implementation.
It also enables designers to choose which peripherals should be attached to the microprocessor and the connectivity between them.
The C/C++ SPE calls a Gnu-based compiler, assembler and linker and enables the development of code targeted to run on platforms created with the MSB.
The Debugger allows the designer to observe and control the execution of the code in both an instruction set simulator (ISS) and in physical hardware.
To help users rapidly evaluate their microprocessor designs in hardware, Lattice provides a LatticeMico32 development kit that includes Lattice's award-winning ispLever software design tools, the LatticeMico32 System development tool suite and a development board.
The board is packed with features that help the designer get maximum value from the hardware evaluation process, including Flash memory for loading programs, optional LCD and keyboard interfaces and a variety of other peripheral interfaces including Ethernet, USB and RS232.
The LatticeMico32 is unique among the microprocessors offered by FPGA vendors in that the generated microprocessor and selected peripheral HDL code are licensed under Lattice's open source licence agreement.
This unique licence allows users to ensure that their proprietary designs remain proprietary and allows the implementation and distribution of hardware without the need for a separate licence agreement.
Additionally, the Gnu-based compiler, assembler, linker and debugger, supplied by Lattice, are released under the standard Gnu General Public Licence (GPL) agreement.
The LatticeMico32 system development tools are available now for the LatticeECP and LatticeEC FPGA families.
The tools can be downloaded at no charge from the LatticeMico32 centre on the company's website.
The LatticeMico32 development kit is available now and is priced at $995.
The kit includes both the ispLever design tools, regularly priced at $695, and the development board, which as a stand-alone is priced at $595.
The kit also can be downloaded from the LatticeMico32 centre.
Lattice expects to release versions of the core optimised for the LatticeECP2, LatticeSC and LatticeXP FPGA families throughout the year.
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