Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeECP2M family'
Edited by the Electronicstalk Editorial
Team on 22 September 2006
Low-cost FPGAs embed high-speed serdes
I/O
The LatticeECP2M FPGA family are the industry's first low cost FPGAs offering high-speed embedded serdes I/O plus a pre-engineered Physical Coding Sublayer block.
Lattice Semiconductor Corp has announced the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded serdes I/O plus a pre-engineered Physical Coding Sublayer (PCS) block Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family also has been developed on advanced 90nm CMOS technology using 300mm wafers
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Previously, high-speed embedded serdes serial I/O with speeds over 3Gbit/s has been available only on relatively expensive high-end FPGAs.
Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment.
Priced at approximately one-third the cost of competitive serdes-based FPGAs, the ECP2M FPGA family effectively bridges the price/performance gap between low cost and high-end FPGAs.
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The LatticeECP2M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, serdes-based applications.
LatticeECP2M Embedded Block RAM capacity ranges from 1.2 to 5.3Mbit, representing up to a 400% increase over competitive low cost architectures.
Both the LatticeECP2 and LatticeECP2M FPGA families offer a comprehensive array of features that includes 375MHz block level performance, 18 x 18 multipliers, embedded memory, pre-engineered 400Mbit/s DDR2 memory interface support, full-rate (above 10Gbit/s) SPI4.2 support, configuration bitstream encryption and dual-boot configuration support.
With the addition of 4 to 16 channels of 3.125Gbit/s serdes, the LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost serdes capability for PCI Express and Ethernet based chip-to-chip and small form factor backplane applications.
"The LatticeECP2M family charts a new course within the low cost FPGA segment, and sets Lattice apart in terms not only of our product innovation but also our ability to bring heightened value to our customers", said Steve Skaggs, Lattice CEO.
"These devices redefine what a low cost FPGA should be, and they will change how customers evaluate FPGAs for their high volume designs".
"Our customers enthusiastically embraced the Economy Plus concept when we introduced it with our first-generation LatticeECP family", said Stan Kopec, Lattice Corporate Vice President of Marketing.
"Now, Lattice is breaking with convention by delivering the lowest cost serdes-based FPGAs in the industry".
"The LatticeECP2M family and our recently announced Extreme Performance LatticeSC devices now provide the industry's most complete portfolio of high-speed embedded serdes solutions".
The LatticeECP2M family will include five devices ranging in density from 20K to 95K look-up tables.
The number of 18 x 18 multipliers in the LatticeECP2M family also has been increased and now ranges from 24 to 168.
Each device provides two delay locked loops (DLLs) and eight phase locked loops (PLLs) for timing control.
The devices will be available in a variety of fine pitch BGA (fpBGA) packages offering 144 to 601 I/O pins and will operate from 1.2V power supplies.
The LatticeECP2M family maintains all of the compelling features of the LatticeECP2 family, including DSP functionality, that are required for high-volume, cost sensitive applications.
The serdes integrated into the LatticeECP2M has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100mW) quad-based architecture with 1 to 4 quads, depending on the size of the device.
Each quad features four serdes channels (four complete Tx and Rx channels) and supports datarates from 270Mbit/s to 3.125Gbit/s.
A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip.
The serdes/PCS combination is designed to support today's most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).
The combination of serdes, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless basestations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable "triple play" technologies.
Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also will benefit from the LatticeECP2M family's unique combination of features.
Design support for the LatticeECP2M devices is provided by the latest version of Lattice's ispLever design tool suite, Version 6.0 SP1.
The ispLever design tools provide access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity.
As with the LatticeSC devices, a convenient module-based GUI (graphical user interface) greatly simplifies configuring the serdes.
Customers also will have easy access to key ispLeverCore intellectual property modules through the IPexpress design flow.
IPexpress-supported functions will include PCI Express, SGMII, DDR1 and DDR2 memory controllers and SPI4.2.
Samples of the first member of the LatticeECP2M family, the LatticeECP2M-35, in both 484 and 672 ball fpBGA packages will be available in October.
Lattice plans to bring the entire LatticeECP2M family to the market during the first half of 2007.
The ECP2M-35 will be priced as low as $22.95 in 100,000 unit quantities for delivery in 2007.
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