Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeECP2/M devices
Edited by the Electronicstalk Editorial
Team on 29 September 2006
Low cost FPGAs turn to display
interfacing
Display interface reference design implements 7:1 source synchronous LVDS interfaces commonly found in display applications.
Lattice Semiconductor has released a free display interface reference design that illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families to implement the 7:1 source synchronous LVDS interfaces commonly found in display applications Lattice also announced its plans for a series of daughter boards that can be used with the existing LatticeECP2 Advanced Evaluation Board to quickly test this reference design for display applications
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
Related stories
Big, fast and wide PLDs in full production
Lattice Semiconductor has announced the completion of the production release of its second-generation SuperFAST BFW (Big-Fast-Wide) family, the ispLSI 2000VE family.
Analogue front end is dynamically reconfigurable
Lattice Semiconductor has added a new member to its ispPAC programmable analogue device family.
By integrating the 7:1 LVDS interfaces within its FPGAs, Lattice enables designers to reduce component count and system cost.
"Our LatticeECP2/M devices offer a compelling value proposition to customers seeking selected high performance features, such as serdes, on a low cost FPGA fabric", said Stan Kopec, Corporate Vice President of Marketing.
"This reference design illustrates how the high performance I/O capabilities of our LatticeECP2/M FPGAs can be used in display applications for the consumer, automotive and industrial instrumentation markets".
Further reading
Software programs analogue devices
Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
In-system reprogrammable 5th-order lowpass filter
Lattice Semiconductor has added to its ispPAC programmable analogue device family with the ispPAC81 in-system programmable continuous time filter.
Display applications require the transfer of large amounts of data across multiple boards within a system.
Often this transfer is implemented with high-speed LVDS interfaces that typically consist of three or four data lines and a clock.
Seven data bits are transmitted for every clock period, and commercially available parts support clock rates of 85MHz and beyond, which translates into datarates of 595Mbit/s and higher.
There are three key challenges associated with implementing high-speed 7:1 LVDS interfaces within FPGAs.
First, a high-speed LVDS buffer is required.
Secondly, high-speed data streams need to be serialised and deserialised.
Thirdly, the skew between data and clock bits must be managed in order to avoid eroding the timing margin.
The display interface reference design takes advantage of the LatticeECP2/M devices' pre-engineered components that simplify the implementation of 7:1 LVDS interfaces.
The LatticeECP2/M FPGAs contain integrated LVDS receivers and drivers capable of 840Mbit/s performance.
Built-in gearbox logic allows a 4x reduction in datarate before the data enters the Look-up Tables (LUTs) at the core of the FPGA.
Built-in edge clocks minimise the skew between data and clocks.
These pre-engineered components allow 7:1 LVDS interfaces to be easily constructed, without the need for manual placement of LUT logic within the devices.
The components also provide more timing margin, which permits a more robust and manufacturable design.
To facilitate testing and evaluation of the LatticeECP2/M devices in display applications, Lattice will make a set of daughter cards available for use with its LatticeECP2 evaluation board.
These daughter cards will allow image data from a source device, such as a DVD player or PC, to be passed through other vendors' devices and ultimately be converted into 7:1 LVDS format before being passed though a cable to the LatticeECP2 board.
The LatticeECP2 device receiving the data then performs simple image manipulations and passes the data off the board, again using a 7:1 LVDS format.
A final board converts the 7:1 LVDS data into DVI format, which is then passed to a display.
The high-speed LVDS display interface reference design is available now for free download from the Lattice website.
The display interface daughter cards designed for use with the LatticeECP2 evaluation board will be available for purchase in Q4 2006.
• Lattice Semiconductor UK: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
