Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeSC family
Edited by the Electronicstalk Editorial
Team on 24 October 2006
Extreme FPGAs gain Serial RapidIO
support
Mercury Computer has ported its high-performance Serial RapidIO IP product line, to the LatticeSC family of 90nm Extreme Performance FPGAs.
Mercury Computer has ported its high-performance Serial RapidIO intellectual property (IP) product line, consisting of x1 and x4 endpoint IP cores, to the LatticeSC family of 90nm Extreme Performance FPGAs In addition, Mercury has joined Lattice's ispLeverCore Connections IP partner programme
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Working together, Mercury and Lattice will develop and deliver complete system solutions for mutual customers requiring high-performance Serial RapidIO connectivity supported by Lattice's FPGA product families.
Mercury achieved its target performance of 12.5Gbit/s with a comfortable guardband on the LatticeSC family by taking advantage of the clock boosting technology incorporated within Lattice's ispLever version 6.0 SP1 software design tool suite.
This feature automatically optimises setup and clock-to-output times in register-to-register paths to improve timing performance.
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The Mercury core also takes advantage of the Serial RapidIO protocol support embedded in the LatticeSC devices' powerful Physical Coding Sublayer (PCS), specifically the complete PCS/PMA layers of the Serial RapidIO Rev 1.2 specification blocks.
"Our partnership with Mercury underscores Lattice's continued commitment to deliver "More of the Best" solutions to our customers who demand full-featured connectivity coupled with excellent performance and low power", said Stan Kopec, Lattice Corporate Vice President of Marketing.
"Lattice is pleased to work with Mercury, a recognised leader in Serial RapidIO solutions, and we see significant opportunity in many chip-to-chip, board-to-board and system-to-system applications, especially where multiple protocols are involved".
"The pairing of Mercury's proven world-class Serial RapidIO core with the LatticeSC devices' exceptional FPGA capabilities provides an outstanding platform for new customer designs".
"Mercury's proven Serial RapidIO core, combined with the outstanding serdes performance, low power and built-in hard logic capabilities of LatticeSC FPGAs, delivers a powerful value proposition for Serial RapidIO designers", said Tracy Richardson, Director of the Silicon Solutions Group in the Advanced Solutions business unit at Mercury.
"Our core technology has been extensively deployed in endpoint and switch applications in the networking, communications and embedded markets, all of which require high performance FPGA technology with advanced serdes capability".
"Lattice delivers on these requirements".
A cofounder and steering committee member of the RapidIO Trade Association, Mercury is an IP provider of Serial RapidIO technology, as well as a system solution developer of Serial RapidIO computing platforms for networking, embedded, and storage applications.
It has hardware-validated the x1 and x4 configurations of the core using the LatticeSC communications board with the Lattice LFSC25 device.
These cores operate with significant timing margin in lower cost LatticeSC speed grades, so designers can optimise system cost and be confident they can easily implement the cores to meet timing requirements in the most demanding applications.
Over the last two years, Mercury has established itself as the leading provider of system-level IP for Serial RapidIO interfaces, and has successfully demonstrated IP working in a range of silicon technologies, including FPGA, structured ASIC and ASIC.
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