Tool suite expands FPGA design capabilities

The latest version of the ispLever programmable logic design tool suite features new design resources and productivity enhancement tools for designers.

The latest version of the ispLever programmable logic design tool suite from Lattice Semiconductor Corp features new design resources and productivity enhancement tools for designers, including the innovative HDL Explorer tool that helps manage and analyse large FPGA designs.

The ispLever 6.1 release supports Lattice's latest FPGAs, including the new LatticeECP2M FPGA family, the new LatticeMico32 System for 32bit microprocessor design and enhanced third-party synthesis and simulation tools.

Combined with numerous other improvements, the ispLever 6.1 tool suite is an extremely powerful programmable logic design solution.

"We're excited to deliver this new tool suite in support of our revolutionary Lattice ECP2M low cost FPGA family with best-in-class memory and serdes capability", said Stan Kopec, Corporate Vice President of Marketing.

"Coupled with our new 32bit open source LatticeMico32 microprocessor and the new PCI Express hard IP solution in our LatticeSC family, it's easy to see why Lattice has 'more of the best' FPGA solutions that are winning over new customers".

Chris Fanning, Corporate Vice President of Software and IP solutions, said: "The ispLever 6.1 tool suite extends its industry-leading timing closure capability and delivers productivity enhancements such as HDL Explorer that enable FPGA designers to complete their designs in an easy-to-use and efficient manner".

"Synplicity's market-leading Synplify Pro software allows designers to take full advantage of the new high-performance LatticeSC devices and the expanded memory in the LatticeECP2M FPGAs", said Joe Gianelli, Synplicity VP of Business Development.

"We believe that the Synplify Pro software's QoR, runtime and ease of use advantages will provide Lattice customers with best-in-class performance as well as cost and time to market benefits when used with these new FPGAs".

"We are very excited about the capabilities of the new LatticeECP2M and LatticeSC families, and what they mean for our mutual customers", said Simon Bloch, General Manager, Mentor Graphics Design Creation and Synthesis Division.

"With Precision Synthesis and the ModelSim Simulator, Mentor Graphics is the only EDA supplier supporting the full FPGA design flow".

"We believe that when combined with the Lattice ispLever 6.1 software, it creates a powerful design solution for engineers trying to solve today's problems".

The ispLever 6.1 tool suite continues to deliver industry-leading performance as the design platform for Lattice's new 90nm LatticeECP2/M high performance, low cost FPGA family and the LatticeSC/M Extreme Performance system chip FPGA family.

The LatticeECP2M FPGA family builds on the previously released LatticeECP2 architecture, but adds the industry's first 3.125Gbit/s serdes capability and the most dedicated embedded RAM resources in a low cost FPGA.

In addition to previously supported Gigabit and 10Gbit Ethernet MAC, DDR I/II, and SPI4.2 hard IP cores, ispLever 6.1 includes new PCI Express MAC support for the LatticeSCM family, which enables the integration of pre-engineered, high-performance IP blocks that reduce design time and cost.

Included with the ispLever 6.1 tool suite, the LatticeMico32 System is used to implement the LatticeMico32 soft microprocessor and attached peripheral components in a Lattice FPGA.

The LatticeMico32 core is a 32bit Harvard, RISC architecture soft microprocessor and is available without charge for customers through an open IP core licensing agreement.

The LatticeMico32 System is based on the Eclipse C/C++ development tools (CDT) environment, an industry open-source development and application framework for building software.

The LatticeMico32 System comprises two integrated tools that provide a complete solution for microprocessor design.

The Mico System Builder (MSB) generates platform description and associated HDL for hardware implementation.

GUIs help the designer choose peripheral components to attach to the LatticeMico32 microprocessor and specify the connectivity between them based on the industry-standard Wishbone bus.

The Software Project Environment (SPE) and debugger help the designer develop and debug code that runs on platforms created with the MSB, including program compilation, assembly, linking and debug.

New with the ispLever 6.1 release, the HDL Explorer tool integrates design creation, analysis, verification and documentation capabilities in a highly customisable HDL analysis environment.

The HDL Explorer tool generates graphic representations of a design's hierarchical structure and connectivity based on the source HDL.

The HDL Explorer tool is particularly useful for IP integration, design maintenance and re-engineering of complex FPGA HDL designs, and also helps the designer visualise higher-level abstractions of the design structure, greatly reducing the amount of time required for design management and documentation.

The HDL Explorer tool also helps the designer produce higher quality code with "linting" technology to detect common design rule faults that can, for example, cause mismatches between pre- and post-synthesis behaviour.

Lattice works closely with its partners Synplicity and Mentor Graphics to provide best-in-class synthesis and simulation solutions as standard features in the ispLever design flow.

The ispLever 6.1 release includes the latest updates to Synplify for Lattice 8.6.2b from Synplicity and Precision RTL 2006a.376 from Mentor Graphics.

An update to the ModelSim 6.2C release also is included.

The Windows-based ispLever 6.1 software that supports all Lattice digital programmable logic families is list priced an industry best value of $695 and is available now.

Unix and Linux versions also are available.

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