Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: IspClock5300S family
Edited by the Electronicstalk Editorial
Team on 01 November 2006
Programmable clock buffers have more
outputs
In-system-programmable zero-delay single-ended clock buffer family expands with 16- and 20-output devices.
Lattice Semiconductor has expanded its ispClock5300S family of in-system programmable, zero-delay, single-ended clock buffer devices with the production release of the pin-compatible ispClock5316S (16-output) and the ispClock5320S (20-output) ICs The E2CMOS-based ispClock5300S device family now offers programmable clock skew, termination and interface standard support in a series of five devices with four to 20 outputs
This article was originally published on Electronicstalk on 21 Jun 2006 at 8.00am (UK)
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"Our ispClock5300S family provides ideal low-cost clock distribution devices for any microprocessor-based system", said Stan Kopec, Lattice Corporate Vice President of Marketing.
"Using a single chip to fan out all clocks from a single source avoids timing issues due to cascading".
"With these new devices, the ispClock5300S family now can address all clock distribution applications which require zero delay buffers and fan-out buffers with up to 20 outputs".
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The ispClock5300S devices support four operating configurations, including zero-delay buffer mode, combined zero-delay and nonzero-delay fan-out mode, dual fan-out buffer mode and fan-out buffer mode with output dividers.
The ispClock5300S family allows each pin to be individually configured, which enables a simple programmable solution that can be customised to suit the design requirements of each circuit board.
The programmable interface type, skew, termination and slew rate features further reduce design effort and result in reduced board space as well as improved board manufacturability and reliability.
Designers now are able to standardise on the ispClock5300S family for all their clock distribution needs, rather than using disparate clock distribution devices from different vendors.
Consequently, inventory is more easily managed and costs are further reduced.
The ispClock5300S devices use three, 5bit on-chip output counters to generate up to three clocking frequencies derived from one reference.
Output clock frequencies can range up to 267MHz.
The high-performance universal fan-out buffer has a maximum pin-to-pin skew of 100ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 70ps and the period jitter is less than 12ps (RMS).
The output skew of each clock net relative to the reference input can be controlled further in delay increments of 156ps (lead or lag) to compensate for differences in circuit board clock network trace length.
The universal fan-out buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels on the outputs, while reference inputs support single-ended or differential inputs.
The input termination and output impedance of each output can be individually tuned to match each trace impedance, which results in clock nets with high signal integrity.
The ispClock5300S devices can integrate multiple types of clock distribution ICs such as zero-delay buffers, fan-out buffers and translators, so designers can easily select the features needed for each individual output pin in their application.
In addition, the reference clock input integrates the necessary termination resistors, simplifying interfaces to popular single-ended as well as differential logic interface standards such as LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL, differential HSTL and differential SSTL at a variety of voltage levels.
Traditionally, clock network designs are constrained to maintain equal clock trace lengths to ensure timing integrity using serpentine patterns to accommodate the extra length clock traces.
Because the outputs of the ispClock5300S devices can be skewed precisely in 156ps increments, designers can route clock patterns more conveniently and compensate for the clock edge arrival delay by skewing each output at the device.
To meet strict EMI standards, designers have commonly resorted to using spread spectrum clocks, which intentionally introduce jitter to diffuse peak power emissions due to coincident clock edge across multiple devices.
However, the increased jitter in the clock is frequently not desirable.
The fine output skew feature of the ispClock5300S devices enables designers to stagger the clock edge in steps of 156ps, allowing the clocking edge to be spread without introducing jitter: a superior method for EMI emission reduction in many applications.
The Lattice Windows-based mixed-signal software design tool, PAC-Designer Version 4.9, provides comprehensive support for all ispClock5300S devices.
Design configurations can be downloaded quickly via the PC parallel port.
This version of the PAC-Designer software can be downloaded for free from the Lattice website.
Prices for the ispClock5316S device and ispClock5320S device start at US $3.80 and $4.10, respectively, in 10,000-unit quantities.
Both devices are available immediately in a pin compatible 64-pin TQFP package in both commercial (0 to +70C) and industrial (-40 to +85C) temperature grades.
PAC-SystemCLK5312S evaluation kits can be used with all five family members and are available through authorised Lattice distributors or on the Lattice website for $295.
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