Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: Latice ECP2O-50 and ECP2-12 FPGA
Edited by the Electronicstalk Editorial
Team on 15 March 2007
FPGAs have DDR interfaces to synchronous
DRAM
FPGA's Double Data Rate 2 (DDR2) Synchronous DRAM memory interfaces operate at 533Mbit/s.
Lattice Semiconductor's ECP2O-50 and ECP2-12 FPGA devices have been fully qualified and released to volume production The second-generation Lattice ECP2 "EConomy Plus" Field Programmable Gate Array (FPGA) families have been produced on 90nm Fujitsu CMOS technology using 300mm wafers
This article was originally published on Electronicstalk on 23 Mar 2001 at 8.00am (UK)
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Final characterisation also confirmed the operation of the devices' Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) memory interfaces at 533Mbit/s, thought to be the industry's fastest rate in a low-cost FPGA.
"The overriding objective for our Lattice ECP2 products has been to combine high performance with low cost", says Stan Kopec, Corporate Vice President of Marketing.
"It is especially exciting to deliver 533Mbit/s DDR2 performance in our low-cost FPGAs as they are production released, a capability two speed grades ahead of competitive low-cost devices".
Further reading
Software programs analogue devices
Lattice Semiconductor has announced manufacturing software support for its revolutionary ispPAC in-system programmable analogue circuit family of devices.
Bigger CPLDs come onstream
Lattice Semiconductor has announced the immediate availability of the first device in its ispMACH 5000VG SuperBIG CPLD family, the 1024-macrocell ispMACH 51024VG.
The Lattice ECP2 devices have been optimised to deliver the features and cost structure required by designers for high-volume system applications, including an optimised logic and routing fabric; pre-engineered 840Mbit/s parallel I/O; pre-engineered DDR2 (now up to 533Mbit/s) memory interfaces; and full feature sysDSP Blocks.
The overall family consists of a total of six logic densities, ranging from 6K to 70K LUTs available in six popular package configurations.
The LatticeECP2 Family also provides other value-added features that are either not available in competitive FPGAs, or require the customer to use higher cost devices, including dual-boot and transparent field reconfiguration (TransFR) I/O support for easy field logic updates, as well as bit stream encryption with on-chip non-volatile key storage for enhanced design security.
Design support for the LatticeECP2 devices is provided by the latest version of the ispLEVERa tool suite, Version 6.1 using Service Pack 2.
The ispLEVER tools provide designers with access, in one software package, to all Lattice digital devices and include synthesis and simulation support from Mentor Graphics and Synplicity at no additional charge.
An extensive range of IP (Intellectual Property) cores, particularly suited for high volume applications, is available for these devices from both Lattice and its IP partners.
The LatticeECP2-50 and LatticeECP2-12 devices are available now in commercial and industrial temperature range options.
The entire LatticeECP2 FPGA family is expected to be production released over the next quarter.
These devices are available in several low-cost packaging options supporting pin-compatible footprints throughout the family for easy density migration.
Pricing in 100,000 piece quantities for the LatticeECP2-50 for delivery in 2H 2007 starts at US $21.00.
The Memory Controller Intellectual property (IP) core for 533Mbit/s DDR2 is available immediately.
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