Programmable logic design suite is free to use

ispLever Classic is a comprehensive software design tool suite that supports all mature Lattice programmable devices.

Available now from Lattice Semiconductor, ispLever Classic is a comprehensive software design tool suite that supports all mature Lattice programmable devices including: GAL and ispGAL simple PLDs (SPLDs); ispLSI, MACH, ispMACH and ispXPLD complex PLDs (CPLDs); Orca, FPSC and ispXPGA field programmable gate arrays (FPGAs); and ispGDX and ispGDX2crosspoint devices.

A Windows-based version of the new software package is available for download and licence at no charge on the Lattice website.

"The ispLever Classic design environment, based on Version 6.1 of our ispLever software design tool suite, is the result of over a thousand man-years of development effort", said Chris Fanning, Corporate Vice President of Software and IP Solutions at Lattice.

"This Classic software design package will provide stable and continuing support for our older, high volume silicon products, even as we continue to develop the system-on-chip design capabilities in our standard software suite that are needed to support 65nm FPGAs and beyond".

"The reprogrammable nature of our products makes the need for long term design support imperative", said Stan Kopec, Corporate Vice President of Marketing at Lattice.

"Lattice is committed to providing accessible, quality design support for our silicon devices throughout their life cycle".

"Our ispLever Classic design tools will ensure our customers can continue to generate and update designs for these established device families".

The ispLever Classic design software is based on the complete ispLever software design tool suite, a comprehensive design environment for all Lattice programmable logic products.

It includes a powerful set of software tools for all design tasks, including project management, HDL design entry, module/IP integration, place and route, timing analysis, in-system logic analysis and much more.

The ispLever Classic design software includes everything necessary to take a project from concept through to a programmed device.

Lattice also works closely with industry leaders Mentor Graphics and Synplicity to provide superior HDL synthesis and simulation solutions, fully integrated into the ispLever design flow.

Lattice's Windows-based ispLever Classic design tool suite is available for download now at no charge from the Lattice website.

Unix and Linux versions of ispLever Classic design software on hard media will be available directly from Lattice.

The downloadable Windows version consists of five modules.

These include: the primary module (supporting CPLD, SPLD products); an FPGA module; a precision RTL synthesis module (from Lattice's partner Mentor Graphics); Synplify for Lattice Synthesis Module (from Lattice's partner Synplicity); and the ispLever Classic help and documentation module.

For user convenience, ispLever Classic also will be included on CD-ROM with future releases of Lattice's ispLever design tools.

In the future, these standard ispLever software packages will provide support for all currently available Lattice 130 and 90nm devices, including the LatticeEC, LatticeECP, LatticeXP, LatticeECP2, LatticeECP2M, LatticeSC and MachXO device families.

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