Product category:
Programmable Logic Devices
News Release from: Lattice Semiconductor UK | Subject: LatticeXP2
Edited by the Electronicstalk Editorial
Team on 31 May 2007
Nonvolatile FPGAs promise more for less
Third generation nonvolatile FPGA family doubles maximum logic capacity, improves performance and adds dedicated DSP blocks.
Lattice Semiconductor has released its third generation of nonvolatile FPGAs, the LatticeXP2 family With enhanced capabilities, the LatticeXP2 family doubles maximum logic capacity to 40K look-up tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%
This article was originally published on Electronicstalk on 28 Jun 2007 at 8.00am (UK)
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This latest product announcement comes over two years after the introduction of the previous generation 130nm LatticeXP family and demonstrates Lattice's ongoing commitment to leadership in the nonvolatile FPGA segment.
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With over 20 years of experience in the nonvolatile programmable logic arena, Lattice's market experience has demonstrated repeatedly that as the premium charged for a nonvolatile solution is reduced at each new process node, significantly more users will take advantage of the benefits of nonvolatility.
"FPGA designers have enthusiastically accepted our prior generation, the LatticeXP Flash-based FPGA family, with thousands of cumulative design-ins worldwide to date", says Stan Kopec, Corporate Vice President of Marketing at Lattice Semiconductor.
"We're gratified that this success has attracted the attention of one of our larger competitors who has recently attempted to jump on the nonvolatile bandwagon, albeit with hybrid, multi-die devices that do not deliver the full advantages of our nonvolatile FPGAs".
"The broad array of enhancements found in our new LatticeXP2 nonvolatile FPGAs, reflecting our 'more of the best' philosophy, is the result of our ongoing dialog with designers who have used our LatticeXP devices".
"With enhanced features and lower prices, LatticeXP2 devices will further expand the use of nonvolatile FPGA technology and accelerate the growth of this increasingly important segment of the FPGA market".
The LatticeXP2 family consists of five members, with capacities from 5K to 40K four-input look-up tables (LUTs).
Embedded block memory provides up to 885Kbit in 18Kbit dual-port blocks.
For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks.
To support increasingly common DSP applications, up to 12 sysDSP blocks provide hardwired high-performance pipelined multiply and accumulate functions.
The devices have up to four phase locked loops (PLLs) that allow designers to align and synthesise clocks as required in their designs.
With power consumption such an increasing concern today for system designers, Lattice designed the LatticeXP2 family to use a 1.2V core voltage for low power consumption.
In addition, the circuit design was tuned to reduce static power per logic function by approximately 33% overall.
This means that while the largest device density has doubled to 40K LUTs compared with the 20K LUTs on the largest LatticeXP2 density, the static power consumed by the largest LatticeXP2 family member has increased by only 34%.
I/O capacities for the family range from 86 to 540 pins.
Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS.
These buffers are supported by pre-engineered I/O logic that simplifies the implementation of double datarate (DDR) and source synchronous standards.
This combination provides support for DDR2 memory interfaces at 400Mbit/s, high performance ADC/DACs at up to 750Mbit/s and 7:1 LVDS display interfaces at above 600Mbit/s.
LatticeXP2 devices are available in a number of space saving chip scale ball grid array (csBGA) packages, thin as well as standard fine pitch ball grid array (ftBGA and fpBGA) packages and popular TQFP and PQFP options.
Flash memory blocks are embedded within LatticeXP2 FPGAs to store the device configuration, providing a true single chip solution that Lattice calls the flexiFlash architecture.
At power up or on user command, the data stored in the Flash memory is transferred into SRAM cells that control the configuration of the device.
This transfer is done in a massively parallel fashion, enabling the device logic to be available in approximately 1mS, well ahead of the other devices in the system and much faster than SRAM-based FPGAs that use external boot PROMs, regardless of whether they are provisioned separately onboard or stacked in the same package.
This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.
By keeping the configuration bitstream on-chip, the LatticeXP2 devices are also inherently more secure than alternative multiple device or multi-chip module solutions.
This security is enhanced by configuration read-back protection modes.
A 64bit erase/program lock protects against accidental or unauthorised device programming.
A one time programmable (OTP) mode is provided for ultimate protection against unauthorised programming.
Optional 128bit AES encryption can be used to secure programming data being passed into the device.
The devices support up to 885Kbit of FlashBAK memory.
This exclusive capability allows embedded block RAMs to be initialised at power up from Flash memory.
During device operation, designers can also choose to write updated data from the block RAM back into the Flash memory.
This provides a method to store data such as power on self test (POST), microprocessor code and calibration data.
An additional 0.6 to 3.3Kbit of Flash memory is provided in the form of serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.
Increasingly, electronic equipment is designed to support field updates and bug fixes.
It is critical that these updates are done reliably, securely and, in many cases, without interrupting equipment operation.
The LatticeXP2 devices address these three requirements.
To protect against incomplete new configuration downloads due to communication or system failures during field updates, a "golden configuration" can be stored in an optional external SPI boot memory and the LatticeXP2 device can boot automatically from this configuration if bitstream errors are detected.
An on chip, user defined 128bit AES decryption key and associated circuitry allows programming data to be encrypted and securely sent to the device remotely, preventing program intercept and piracy.
The devices also support TransFR (transparent field reconfiguration) technology that allows new configurations to be loaded into the LatticeXP2 device while the I/O states are precisely controlled, allowing new configurations to be applied while the overall equipment continues to operate.
Concurrent with the announcement of the LatticeXP2 family, Lattice is also releasing a new generation of its ispLever design tool suite, ispLever version 7.0 (please see the separate ispLever press release dated today).
In addition to providing design support for theLatticeXP2 family, the version 7.0 release provides major general enhancements including substantial speed and utilisation improvements for all Lattice FPGA families, a greatly enhanced Power Calculator module, the entirely new Reveal design analysis tool with the industry's most advanced logic analysis triggering capabilities and many other enhancements.
IspLever version 7.0 will be shipped by the end of June to all Lattice registered software users on maintenance contract.
Samples of the first member of the LatticeXP2 family, the 17K LUT LatticeXP2-17, in 208PQFP, 256ftBGA and 484fpBGA packages are available now.
Lattice plans to bring the entire device family to market during 2007.
The LatticeXP2-17 will be priced as low as US $12.00 in 100,000 unit quantities for delivery in 2008.
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