Product category:
Design and Development Software
News Release from: Lattice Semiconductor UK | Subject: IspLever
Edited by the Electronicstalk Editorial
Team on 22 April 2008
FPGA design tools add mixed language
simulator
Active-HDL Lattice Edition will be bundled with the next version of Lattice's ispLever design tool suite.
Lattice Semiconductor and Aldec have signed an OEM agreement that will deliver the only OEM FPGA mixed language simulator Active-HDL Lattice Edition will be bundled with Lattice's ispLever design tool suite, providing mixed language simulation (VHDL, Verilog and SystemVerilog), cosimulation with Simulink from The MathWorks and simulation support for Lattice encrypted IP cores
This article was originally published on Electronicstalk on 24 Apr 2002 at 8.00am (UK)
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The simple machine for complex design
"The simple machine for complex design" is the description given by Lattice Semiconductor to its next-generation ispLever design tools.
The simple machine for complex design
Dubbed "The simple machine for complex design", the latest generation of the ispLever design tool provides developers a simple powerful tool to use with all of Lattice's programmable logic products.
"We're excited to partner with Lattice and bundle our powerful mixed language simulator with Lattice's FPGA solutions", says David Rinehart, Vice President of Marketing at Aldec.
"Active-HDL Lattice Edition is derived from an industry-proven FPGA solution that offers the performance and functional capabilities that Lattice FPGA designers increasingly require to efficiently verify their designs".
Chris Fanning, Corporate Vice President, Enterprise Solutions, adds: "Our alliance with Aldec enables Lattice to offer exceptional design verification capabilities that deliver incomparable value when bundled with our ispLever design tool suite".
Further reading
Programmable designs keep track of revisions
Lattice Semiconductor has released a powerful new generation of its ispLever design tool suite.
Approved cores speed programmable system design
The ispLeverCore Connection marks a new level of collaboration between Lattice and independent developers of intellectual property.
"Our alliance with Aldec marks another milestone in Lattice's commitment to deliver industry leading solutions to our FPGA customers".
Active-HDL Lattice Edition boasts high performance simulation for Lattice designs, mixed HDL language support and a host of productivity enhancers ranging from testbench generation from a graphical waveform to co-simulation with The MathWorks Simulink.
Active-HDL Lattice Web Edition is designed for single language simulation, either VHDL or Verilog, and smaller designs more typical of devices supported by the ispLever Starter and ispLever Classic tools.
The ispLever design tool suite is the flagship design environment for the latest Lattice FPGA products.
It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis, and more.
The ispLever suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms.
ispLever Windows includes industry leading third party tools from Lattice partners Synplicity and Aldec for synthesis and simulation.
Active-HDL Lattice Edition will be bundled with the next version of Lattice's ispLever design tool suite.
Active-HDL Lattice Web Edition will be made available free of charge via the Lattice website to support the many users of Lattice's ispLever Classic and ispLever Starter design tools.
Lattice's ispLever 7.1 for Windows, including Aldec Active-HDL Lattice Edition, will be available without charge for customers with active design tool maintenance contracts.
The price of the full ispLever design tool suite starts at US $895 for the Windows version.
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