Design suite bundles industry's best FPGA tools

Latest FPGA design tools deliver up to 30% faster design compile times and support multiprocessor powered design compilation to achieve the fastest timing closure.

Lattice Semiconductor has released a new version of its ispLever FPGA design tool suite.

The new tool release delivers a number of new functional and performance-enhancing features, including the industry's first dedicated FPGA simultaneous switching output (SSO) analyser.

The SSO analyser enables FPGA designers to actively analyse and optimise I/O pin placement and output switching characteristics to minimise undesirable noise and ground bounce on a printed circuit board.

To enable designers to achieve higher levels of productivity, the ispLever 7.1 design tools also deliver up to 30% faster FPGA design compile times and now support multiprocessor powered design compilation to achieve the fastest timing closure.

According to Chris Fanning, Corporate Vice President, Enterprise Solutions: "Lattice's highest design tool priority continues to be delivering industry leading timing closure capability to FPGA designers".

"The ispLever design tool suite now delivers industry leading performance and innovative productivity tools that enable FPGA designers to optimise their designs more productively and efficiently".

An enhanced power calculator enables FPGA designers to analyse and optimise power requirements early in their design.

The Lattice power calculator includes an exceptionally user-friendly interface that enables power analysis at the block level and examination of "what-if" scenarios by changing design environment variables.

This release marks the addition of Synplicity's Synplify Pro and Aldec's Active-HDL Lattice Edition as principal elements of the ispLever FPGA design flow.

"We're excited about our new OEM tool bundle", says Tim Schnettler, Director of Design Tools Marketing at Lattice.

"Lattice now offers the very high performance, mixed language design flow that today's complex designs demand".

The ispLever 7.1 release marks a new standard in performance, encompassing improvements in post-route design operating frequency of up to 5% and runtime reductions by as much as 30% for larger designs.

These improvements decrease costs, speed-timing closure and help users deliver the best solutions more quickly.

A recent release of the LatticeMico32 embedded processor solution included Linux O/S-based tools, VHDL language support (through VHDL wrappers of the Verilog IP) and added arbitration support.

The ispLever 7.1 release seamlessly integrates the LatticeMico32 Mico System Builder into its design flow.

The new arbitration support automatically selects the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated, enabling shared-bus or slave-side arbitration.

This capability allows multiple master ports efficient access to multiple slave ports.

Lattice also has recently added the uClinux O/S to a portfolio that already included RTOS support from Micrium and uItron.

The release of ispLever version 7.1 is the first that includes the latest LatticeMico32 support.

The ispLever design tool suite is Lattice's flagship FPGA design environment for use with its latest FPGA products.

It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, timing analysis, place and route, in-system logic analysis and more.

The ispLever tool suite is provided on CD-ROM and DVD for Windows/Vista, Unix and Linux platforms.

The new OEM agreement between Aldec and Lattice enables Lattice to bundle the Active-HDL Lattice Edition with its ispLever suite, and Active-HDL Lattice Web Edition with Lattice's ispLever Starter and ispLever Classic design tool suites.

Active-HDL Lattice Edition features mixed language simulation of VHDL and Verilog, co-simulation with The MathWorks Simulink, and many advanced verification and debug features such as language assistant, code execution tracing, advanced breakpoint management and memory viewing.

Synplify Pro will now be bundled with the ispLever design tool suite and will deliver a number of advanced synthesis features to Lattice FPGA designers, including mixed VHDL and Verilog synthesis, automatic register balancing and HDL-Analyst.

Standard Synplify will continue to be available for use with Lattice ispLever Starter and ispLever Classic design tools.

Lattice's ispLever 7.1 for Windows, Linux and Unix users is available immediately without charge for customers with active design tool maintenance.

The full ispLever design tool suite starts at a price of US $895 for the Windows version.

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