Product category:
Intellectual Property Cores
News Release from: Lightspeed Logic | Subject: LTA90
Edited by the Electronicstalk Editorial
Team on 14 May 2007
Reconfigurable logic IP cuts SoC design
costs
Standard cell based reconfigurable logic IP runs on TSMC's 90nm G, LP and GT logic processes.
Available now from Lightspeed Logic, the leading provider of mask reconfigurable IP and a member of the ARM Connected Community, the LTA90 is a standard cell based reconfigurable logic IP for TSMC's 90nm G, LP and GT logic processes The 90nm standard tile and library are based on precharacterised, prequalified ARM standard cell libraries, part of its family of Artisan physical IP, and are approved for use by any ARM authorised customer using TSMC as a foundry
This article was originally published on Electronicstalk on 24 Dec 2002 at 8.00am (UK)
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Manufacturability-optimised reconfigurable logic intellectual property brings significant benefits to customers designing in advanced geometries.
Lightspeed Logic's reconfigurable logic IP significantly reduces design cost and speeds time to market for families of SoC or ASSP devices.
Customer usage includes such high volume markets as image processing, handheld consumer, and flat panel TV.
"Lightspeed Logic's new TSMC 90nm ARM standard cell-based reconfigurable logic solution provides SoC and ASSP chip designers with flexible and scalable IP built on the industry's leading standard cell library for the industry's most popular foundry", said Dave Holt, President and CEO of Lightspeed Logic.
"Chip designers get the quality, performance and low-risk profile of an ARM standard cell solution in a mask-reconfigurable format utilising their existing tool flow".
"This provides superior density and performance for high-volume chip families at much lower design cost and in shorter design times than can be accomplished with traditional methodologies".
Lightspeed Logic's Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80% the density of traditional methodologies for multi-million-gate logic blocks, twice the density of competing mask reconfigurable solutions.
The LTA90 is available for design blocks ranging from 50,000 gates to 5 million gates.
The LTA90 also offers designers the flexibility to choose the number of mask layers to be used for customisation on a device-by-device basis, without change to the underlying logic array.
Typical customisation usage models range from two to six metal/via-mask pairs.
The LTA90 supports speeds up to 300MHz for 25 levels of logic.
The 90nm product is an addition to Lightspeed Logic's LTA130, a 130nm tile-based reconfigurable logic for TSMC processes that also uses ARM standard cells.
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