Product category:
Intellectual Property Cores
News Release from: Lightspeed Logic | Subject: Manufacturability-optimised reconfigurable logic
Edited by the Electronicstalk Editorial
Team on 19 July 2007
Reconfigurable logic IP optimised for 65
and 45nm
Manufacturability-optimised reconfigurable logic intellectual property brings significant benefits to customers designing in advanced geometries.
Lightspeed Logic has come up with a new generation of reconfigurable logic IP for the 65 and 45nm process nodes In addition to providing increased flexibility in chip architecture, significant reduction in design cost and rapid time to market, the new manufacturability-optimised reconfigurable logic brings significant benefits to customers designing in advanced geometries
This article was originally published on Electronicstalk on 24 Dec 2002 at 8.00am (UK)
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The manufacturability-optimised logic also enables faster process debug and ramp up and delivers higher yields after the process has been stabilised.
The addition of these new capabilities to the already high-density achieved by Lightspeed Logic's reconfigurable logic IP will produce a higher number of known-good dies per wafer and effectively outperform the equivalent density of standard cells.
Lightspeed Logic has been collaborating with the industry's leading DFM solutions provider, Clear Shape Technologies to model the manufacturability of the optimised tiles to achieve the goals described above.
"Lightspeed Logic's approach, combined with our recognised expertise and manufacturing models validated by the leading IDMs and foundries, is providing our customers with an appealing alternative to master the challenges of 65nm and below", says Atul Sharan, President and CEO of Clear Shape.
"Our collaboration brings a unique advantage to designers in addressing nanometre scale semiconductor manufacturing challenges".
"At 65 and 45nm, Lightspeed Logic's manufacturability optimised reconfigurable logic delivers a yield breakthrough, with yielded die surpassing that of traditional standard cell methodology", says Dave Holt, CEO of Lightspeed Logic.
"This combined with increased performance and the increased flexibility in chip architecture, significant reduction in design cost, and rapid time to market, are a part of the innovation engine allowing the semiconductor industry to continue to keep pace with Moore's Law".
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