Design-for-test tool runs at-speed

LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs.

LogicVision has unveiled its ScanBurst tool and has partnered with Mentor Graphics to deliver a unique and improved at-speed test solution for high-speed nanometre designs.

This new integrated solution combines Mentor's world-class automatic test pattern generation (ATPG) and embedded compression products, FastScan and TestKompress, with LogicVision's new ScanBurst tool to improve the accuracy and effectiveness of at-speed test, enabling better and more efficient detection of subtle delay defects that are prevalent in today's nanometre SoC designs.

A major issue faced by SoC design teams adopting 90 and 65nm process nodes is the increase in yield fall out.

At 90nm it is estimated that 30% of yield fall out is due to performance and signal integrity issues.

As a result, accurate and cost effective at-speed manufacturing test and characterisation has become evermore critical to achieve high quality silicon.

Traditional at-speed test approaches have proven inaccurate in identifying subtle performance issues, resulting in potential test escapes or overly optimistic device performance characterisation.

ScanBurst is a new and innovative at-speed DFT (design-for-test) tool from LogicVision designed specifically to overcome the limitations of traditional at-speed DFT techniques.

ScanBurst is designed specifically to complement existing ATPG based DFT techniques by providing an environment to easily insert scan and clock control structures for at-speed testing based on LogicVision's patented BurstMode timing technology.

ScanBurst is integrated with Mentor's FastScan ATPG and TestKompress embedded compression products, and provides a seamless solution that fits within existing scan-based DFT flows.

"The focus on quality of test, especially through the use of an at-speed test methodology, is mission critical for nanometre design", stated Robert Hum, Vice President and General Manager of Mentor Graphics Design Verification and Test division.

"With Mentor's best-in-class ATPG and compression technology, we are able to team with LogicVision, leverage their unique technology, and provide a substantial competitive advantage for our mutual customers".

"Our customers have told us that they want to take advantage of our proven BurstMode technology in our ETLogic logic BIST solution within their existing Mentor scan ATPG environment", said Jim Healy President and CEO of LogicVision.

"By delivering our at-speed solution in a Scan ATPG environment with Mentor Graphics, we're addressing an unfulfilled need in the market place and helping our joint customers improve their silicon performance characterisation and final product quality".

The traditional approach of testing for performance related defects with ATPG based solutions has been to generate patterns that target transition delay faults.

These patterns are applied using two at-speed functional clock cycles to create a "launch" and "capture" sequence.

This approach is often referred to as "double-capture" timing.

However, the "double-capture" technique often does not correlate well with functional performance resulting in test escapes or yield loss.

In particular it has suffered from what is referred to as "clock stretching".

This phenomenon is caused by the instantaneous drain on power rails during the launch and capture cycles that results in an increase of the clock period, and in an optimistic performance rating of the device, as well as reduced delay fault detection.

The BurstMode timing technology avoids this situation by providing for programmable ramping of the at-speed clock activity before each test capture.

This ensures that the power rails have recovered from the initial instantaneous voltage drop (no clock stretching) and true functional performance parameters are tested.

BurstMode timing is a proven technology that has been in production use at leading semiconductor companies as part of LogicVision's Logic BIST solution.

ScanBurst provides comprehensive design automation for generating and integrating the on-chip distributed clock and scan control logic, which enables the application of BurstMode timing in conjunction with Mentor's FastScan and TestKompress ATPG products.

ScanBurst also enables users to easily and efficiently apply scan patterns in a truly hierarchical fashion.

LogicVision's patented core-isolation-logic greatly simplifies and optimises the generation and application of scan patterns to individual cores.

This provides several significant benefits including reduced test generation times, robust pattern generation and reduced test pattern data volume.

The core isolation technology also enables DFT teams to apply at-speed scan patterns to an arbitrary number of cores, allowing them to trade off test time with average power levels during test.

This capability provides significant advantages when dealing with designs that use elaborate clock-gating schemes to achieve low power consumption.

ScanBurst integrated with Mentor's FastScan and TestKompress tools is available for early customer evaluation immediately.

Full customer availability is scheduled for Q1 of 2007.

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