Product category:
Memory Devices and Modules
News Release from: Logic Devices | Subject: LF3324
Edited by the Electronicstalk Editorial
Team on 12 May 2005
Frame buffer/FIFO features flexible
operation
The LF3324 frame buffer/FIFO leads the industry in density and flexibility by integrating 24Mbit memory with robust addressing capabilities including both sequential and random access modes.
Logic Devices has begun sampling its next-generation LF3324 frame buffer/FIFO The device leads the industry in density and flexibility by integrating 24Mbit memory with robust addressing capabilities including both sequential and random access modes
This article was originally published on Electronicstalk on 24 Dec 2007 at 8.00am (UK)
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This integrated approach simplifies video and data buffering systems that typically use standard random access memories (RAM) paired with field programmable gate array (FPGA) logic.
The new LF3324 features independent input and output data ports along with several addressing modes.
The 24Mbit memory can be accessed sequentially, through random access, or both.
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Flexible addressing modes allow the device to perform first-in first-out (FIFO), shift register and mixed sequential/random access functions.
With a maximum datarate of 74.25MHz, the LF3324 is well positioned to buffer multiple video formats, including HDTV.
Devices can be cascaded to enable even larger word-widths or depths.
A seamless address space is maintained in the random access mode, even when cascading multiple devices for high-resolution images.
The input/output ports are capable of accepting 8, 10 or 12bit data without wasting memory.
Logic Devices is targeting broadcast video equipment, medical imaging, machine vision, video editing systems and security surveillance applications with the new offering.
The device configurability, along with its 74MHz operating speed, provides the designer with unprecedented flexibility in applications requiring storage density, speed, and flexible addressing.
The random access modes facilitate complex addressing schemes such as multiple-queue buffering, image rotation, video compression algorithms, area of interest (AOI) and picture in picture (PIP) extraction.
The FIFO and shift register modes are useful in synchronising multiple video streams or data feeds, frame synchronisation, motion detection, scan rate conversion, motion adaptive de-interlacing, and time base correction (TBC).
The LF3324 is packaged in a 15 x 15mm small form factor 172-pin low profile ball grid array (LBGA) package.
The package will be available in a green version, which meets the joint IPC/JEDEC standard J-STD-020B and complies with European Union requirements scheduled to take effect in 2006.
Commercial temperature grade samples of the LF3324 are immediately available.
Production quantities will be available in the fourth calendar quarter of 2005.
Initial pricing for the LF3324 is $37 each in quantities of 10,000.
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