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News Release from: LSI Europe | Subject: QDR-2 core
Edited by the Electronicstalk Editorial
Team on 13 July 2004
Interface speeds QDR memory access
LSI Logic Corp has developed the industry's highest speed physical layer interface to QDR-2 SRAM memory, enabling the next generation of high-end network routers, switches and host bus adapters.
LSI Logic Corp has developed the industry's highest speed physical layer interface to QDR-2 SRAM memory, enabling the next generation of high-end network routers, switches and host bus adapters Supporting speeds up to 333MHz and 667Mbit/s, the new QDR-2 ASIC core makes it easy for network equipment manufacturers to tap the low latency, high bandwidth capabilities of QDR-2 SRAM for designing terabit-level products with shorter development times
This article was originally published on Electronicstalk on 23 May 2001 at 8.00am (UK)
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LSI Logic's QDR-2 core is a physical layer interface with a special HSTL I/O interface buffer that can be easily integrated on a cell-based ASIC, or a RapidChip platform ASIC for fast system-on-a-chip (SoC) designs.
The QDR-2 is a preverified physical layer interface validated in silicon, which significantly reduces the risk and turnaround time of product development.
"QDR-2 SRAMs are ideal for the high-bandwidth, latency-sensitive applications of terabit-speed telecom and data network gear", said Jean Bou-Farhat, Vice President, CoreWare, LSI Logic.
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"But these high performance memories present new challenges in designing and implementing the physical layer interfaces".
"The QDR-2 core is designed to speed the implementation with ease and complete confidence in a solution that has been tested and validated in silicon".
LSI Logic's QDR-2 cores includes address and data path hard macros with HSTL I/O buffers and provides an integration-friendly physical layer interface between a customer's ASIC memory controller logic and the data and address busses of QDR-SRAM memory.
The core and I/O are available in LSI Logic's Gflx process technology (0.11um) and can operate at datarates up to 667Mbit/s.
The read and write datapaths are 18bit wide and can be used in parallel to build databus widths of 18, 36 or 72bit providing a total bandwidth of 24, 48 or 96Gbit/s, respectively.
The address hard macro is 22bit wide.
If an application requires more address bits, then multiple address hard macros may be used.
The QDR-2 core employs hard macros with preverified functionality, layout and guaranteed timing closure.
The master delay hard macro measures parts of the clock period using precise analogue delay elements and provides a 90-degree delay over PVT.
The read and write datapath hard macros provide a data interface between the controller logic and memory.
The datapath hard macros support data transfers to and from the QDR-SRAM on both edges of the clock, effectively doubling the data throughput.
The QDR-2 core is built to support burst lengths of 2 and 4, programmable delay for read operation, write data phase alignment of 0 or 90 degrees to the output clock, and scan and BIST functions.
The core uses a delay locked loop to maintain constant programmable delay over PVT.
Routing within all hard macros is optimised for operation up to 333MHz or 667Mbit/s across all process, voltage and temperature conditions.
LSI Logic's special HSTL I/O driver and receiver are built to operate at either 1.8 or 1.5V, allowing system designers to switch to future lower power devices.
The HSTL I/O supports multiple impedance modes, driver impedance control, has excellent duty cycle matching and provides an electrical interface of superior signal integrity.
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