Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: LSI Europe | Subject: RapidChip Xtreme2
Edited by the Electronicstalk Editorial
Team on 15 March 2005
Platform ASICs tackle high-speed serial
tasks
LSI Logic Corp has released the RapidChip Xtreme2 family of platform ASICs, which builds on the company's leadership in the RapidChip technology performance and integration capability.
LSI Logic Corp has released the RapidChip Xtreme2 family of platform ASICs, which builds on the company's leadership in the RapidChip technology performance and integration capability The RapidChip Xtreme2 family currently consists of 12 slices and provides the necessary resources for developers to tackle the most demanding high-speed serial applications in the computing, communications, storage, and embedded systems marketplace
This article was originally published on Electronicstalk on 23 May 2001 at 8.00am (UK)
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Integrated resources include up to 48 serdes, up to five million gates and 3.7Mbit of RAM, a flexible MatrixRAM internal memory architecture and support for popular external high-bandwidth memory interfaces such as DDR2 and QDR.
Performance and capabilities previously achievable only in a cell-based ASIC can now be realised quickly and affordably with the RapidChip Xtreme2 platform ASIC family.
"The RapidChip Xtreme2 family incorporates the resources needed to build the sophisticated serial I/O fabrics at the heart of modern IT infrastructure", said Jerry Worchel, Principal Analyst, ASIC/ASSP for In-Stat.
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"Just as important, by making these resources available in a platform ASIC, LSI Logic's customers can innovate and at the same time effectively manage cost, risk and time to market".
Building on LSI Logic's high-speed serial I/O leadership, the RapidChip Xtreme2 family integrates up to 48 GigaBlaze and Hydra serdes in various combinations that satisfy a broad range of applications across multiple markets.
With datarates up to 4.25Gbit/s, supported standards include, but are not limited to, gigabit Ethernet, 10 gigabit Ethernet (XAUI), PCI Express (including ASI), Fibre Channel, InfiniBand, CX4, Serial Rapid IO, SGMII, SPI4.2, SPI5, SAS, SATA, and HyperTransport standards.
"With its flexible architecture and support for full-speed HyperTransport technology, LSI Logic's RapidChip Xtreme2 family is an ideal complement to the AMD Opteron processor", said David Rich, Director of 64bit Embedded Markets at AMD.
"The combination of the AMD Opteron processor with Direct Connect Architecture and LSI Logic's RapidChip technology provides embedded designers with lower development costs and quicker time to market for their high-performance, highly-integrated solutions".
The MatrixRAM architecture consists of one or more densely packed arrays of memory "instances".
Instances are prediffused memory building blocks that can be used individually or can be flexibly combined to form larger memories.
These larger memories can be configured to a wide range of widths and depths to fit whatever an application requires.
Because instances are densely packed and prediffused, routing overhead is low and the resulting memories are extremely fast.
MatrixRAM memory enables system designers to meet many diverse requirements while giving up little in the way of performance or density as compared with a standard cell ASIC.
In addition to high-speed serial interfaces supported by integrated serdes, the "configurable I/O" portion of the RapidChip Xtreme2 family of slices can support a wide variety of high-performance, low-latency parallel interfaces.
Supported memory standards include DDR2, which is emerging as the dominant memory technology in enterprise computing; RLDRAM2 and FCRAM2 common in high performance networking and QDR common in storage networking.
Very fast LVDS buses like SPI-4.2 can be implemented in configurable I/O as well.
By nature high-speed parallel interfaces are extremely timing sensitive, and the RapidChip Xtreme2 family embodies LSI Logic's industry-leading signal integrity expertise with features such as on-die termination, slew rate control, and source impedance control.
"By leveraging our extensive experience in high speed I/O and our proven serdes technology, we're enabling our customers to design robust enterprise and communications infrastructure solutions with an easy-to-use design flow that reduces effort and risk", said Thomas Colino, Director, RapidChip Platform Architecture, LSI Logic Corp.
"Customers also have at their disposal an extensive portfolio of proven intellectual property with cores and tools from LSI Logic, and from third-parties via the RapidChip Platform ASIC Partner Programme".
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