Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: LSI Europe | Subject: Wafer-level packaging
Edited by the Electronicstalk Editorial
Team on 23 May 2005
Wafer-level packaging shrinks SoC
designs
LSI Logic Corporation has released its enhanced wafer-level packaging (WLP) technology for use in ASIC/SoC designs.
LSI Logic Corporation has released its enhanced wafer-level packaging (WLP) technology for use in ASIC/SoC designs Packages produced in this cost-effective, high-performance technology are completely manufactured and tested at the wafer level and then mounted directly onto printed circuit boards or on discrete package substrates
This article was originally published on Electronicstalk on 23 May 2001 at 8.00am (UK)
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WLP offers the industry's lowest cost packaging solution in an ultrasmall form factor with improved electrical performance.
System designers making use of WLP can conserve valuable board real estate while integrating additional features into portable applications such as cellphones, PDAs and other handheld consumer devices.
The flexible WLP design methodology offered by LSI Logic enables a single design to accommodate a variety of package technology formats.
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By only modifying the top metal layer, the chip design can be reconfigured for flip-chip, wire-bond or direct chip attach interconnect solutions.
With this approach, system designers gain considerable design flexibility and intellectual property (IP) re-use with minimal development effort, thereby drastically reducing nonrecurring engineering (NRE) costs and speeding time to market.
"WLP technology broadens the LSI Logic packaging portfolio and enables more flexible system-level design solutions where a small form factor is required", said Stan Mihelcic, Director of Packaging and I/O Marketing at LSI Logic.
"Our unique methodology also provides our customers with the additional flexibility of accommodating either a wire-bond or flip-chip bump interconnect format".
"This is especially important for system designers who require variations of a standard chip design utilising deep-submicron ASIC/SoC technology".
The die in a WLP format can be connected directly to the host system board, eliminating traditional packaging parasitics.
This electrical performance enhancement enables more flexible system-level design solutions for high performance memory interfaces and serialiser/deserialiser (serdes) technology where stringent system timing budgets continue to challenge system designers.
By leveraging existing wafer processing techniques, engineers can co-design and develop an optimal bump layout to suit the particular application.
A typical concern with die only packages has been the ability to provide a fully tested "known good die" (KGD) product.
However, with advanced wafer level test methodologies and wafer level reliability offered by LSI Logic, true KGD products are possible requiring no additional package level final test.
In addition to portable handheld consumer devices, WLP technology also enables new product growth in industrial, medical and military applications that require a small form factor.
LSI Logic supplies ASIC/SoC solutions to these markets.
Customers adopting WLP can make use of standard surface mount assembly techniques without changing existing equipment and processes.
WLP offered by LSI Logic is available in both eutectic and RoHS compliant lead-free solder terminations, eliminating the use of hazardous leaded solder material from the manufacturing process.
WLP solutions are available today in high volumes to LSI Logic customers.
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