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Mentor Graphics UK
Address:
Rivergate, Newbury Business Park
London Road
Newbury
RG14 2QB
UK
Telephone: (UK) +44 1635 811411
http://www.mentor.com/uk
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Listing of all 348 news releases from Mentor Graphics UK:
Debug environment speeds ASIC validation
Isolating the cause of a failing processor driven test is a tedious and time consuming process, as RTL processor models delivered by the core vendor provide little or no debug visibility.
News from Mentor Graphics UK (31 March 2008)
FPGA synthesis accepts VHDL and Verilog
Simulink HDL Coder and Precision Synthesis provide a rapid path from Simulink models to FPGA implementation.
News from Mentor Graphics UK (16 November 2007)
Design kit mixed-mode and logic sub-processes
A packaged RF flow tutorial takes an RF circuit design from schematic capture through RF simulation, layout and post-layout simulation.
News from Mentor Graphics UK (14 November 2007)
Design software offers new compatability
The HDL Designer formulates an optimum design-to-verification environment for creating and managing complex designs using VHDL, C/C++, PSL, Verilog, mixed-languages and now, SystemVerilog.
News from Mentor Graphics UK ( 8 November 2007)
Design companies agree on verification
The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability.
News from Mentor Graphics UK (17 August 2007)
Vehicle electrical design goes collaborative
Combination of KBL and automated change management facilities is an important next step in improving the efficiency of the engineering process.
News from Mentor Graphics UK (15 August 2007)
Control system demonstrates viability of Autosar
User application article Mentor Graphics has completed a demonstrator project for Volvo that entailed completely redeveloping an existing climate control system using Autosar technology.
News from Mentor Graphics UK (19 June 2007)
Acquisition delivers powerful design-to-fab flow
Mentor Graphics Corp has acquired Sierra Design Automation for US $90 million in cash and stock.
News from Mentor Graphics UK (12 June 2007)
Infineon and Chartered use litho-friendly design
User application article Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology.
News from Mentor Graphics UK (31 May 2007)
Mixed-signal flow is proved with UWB transceiver
Mentor Graphics has set up a new reference flow for analogue and mixed-signal SoC designs.
News from Mentor Graphics UK (24 May 2007)
Functional verification expands in scope
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation.
News from Mentor Graphics UK (17 May 2007)
500 companies download datatypes
User application article Mentor Graphics' Algorithmic C (AC) datatypes enable algorithm, system and hardware designers to precisely model bit-true behaviour in C++ specifications while accelerating simulation speeds.
News from Mentor Graphics UK ( 7 May 2007)
Software creates user interfaces for new devices
API delivers a new approach for rapid creation of dynamic user interfaces for electronic devices, enabling manufacturers to deliver visually appealing and easy-to-use electronic-device UI screens.
News from Mentor Graphics UK ( 4 April 2007)
Synthesis software has new Xilinx devices covered
Advanced synthesis products support lastest Virtex-5 SXT FPGAs from Xilinx.
News from Mentor Graphics UK (12 March 2007)
Latest generation of PADS flow PCB design software
The latest generation of PADS flow PCB design software has highly automated functions to implement RF and microwave circuitry and performs design for fabrication checking early in the design process
News from Mentor Graphics UK ( 8 March 2007)
Tools to verify complex mixed-signal chip designs
User application article Leading international chip companies make use of design verification software
News from Mentor Graphics UK ( 6 March 2007)
PCB design flow maintains users' IP investments
Mentor Graphics has announced the release of Board Station XE, the next generation version of its Board Station design flow for large, enterprise customers.
News from Mentor Graphics UK ( 9 February 2007)
Next-generation OPC solution from Mentor Graphics
Calibre nmOPC delivers accuracy and performance with dramatic reduction in cost of ownership for RET flow
News from Mentor Graphics UK ( 4 December 2006)
TSMC-qualified process design kit
Mentor Graphics is releasing foundry-qualified process design kits (Mentor-PDKs) that support Mentor's entire custom/mixed-signal IC design flow.
News from Mentor Graphics UK ( 4 December 2006)
Advanced synthesis products support Stratix III
Mentor's suite of advanced synthesis products now supports Stratix III field programmable gate arrays (FPGAs) from Altera Corp.
News from Mentor Graphics UK (10 November 2006)
Improved analysis of manufacturing failures
Compression software improves ATPG
Ford standardises harness design tools
Advanced synthesis products support latest FPGAs
Router adds intelligence to automation
RTOS kernel is much smaller and faster
Low-power spec becomes open industry standard
RET verification package proves popular
Simulator ensures silicon-patterning success
Comprehensive claims for PCB design suite
Package supports ARM Cortex developments
Synthesis tool cuts C-based design effort in half
Superior productivity on the dual-core xeon 5160
Calibre nmDRC supports the AMD opteron processor
TSMC qualifies Mentor Graphics Calibre nmDRC
Mentor Graphics Calibre nmDRC adopted by UMC
Mentor Graphics and ARM validate physical IP
Reference flow 7.0 includes design for test suite
Award for Design-for-Test Team
Coexisting multiple file system formats supported
Simulation platform integrates speedy Spice
Design rule checker adapts to the nanometre era
Datatypes improve simulation performance
System level tool supports complex designs
Synthesis libraries qualified for ASIC design
Pioneer adopts synthesis tools
DFM technologies are qualified for 65nm process
Harness software integrates with MCAD and PDM
Partnership enhances verification options
Functional verification moves to next generation
Verification platform adopts latest specs
Mentor supports Russian education
Software promises faster route to big boards
Design tools support Common Platform
Translators simplify migration of PCB CAD
Coverification tool supports Diamond series
Mask data toolsuite cuts files down to size
Signal integrity design kits support new standards
Japanese consortium collaborates on test schemes
SystemVerilog pioneers recognised by IEEE
Partner programme supports platform ASIC design
Mentor helps AMD to reference designs
SAIC signs for network design and test tools
MediaTek opts for Spice simulator
Faraday adopts Spice simulator
Verification software cuts costly mask respins
SMIC opts for analogue simulator
Software agreement speeds FPGA design support
Encryption secures process design kits
Chinese telecommunications firm chooses XtremePCB
Diagnostic tool enhances semiconductor yield
Design system takes an enterprise-wide view
Mixed-signal environment speeds automotive ASICs
Full toolset addresses automotive design needs
HDL design suite gains its own spellchecker
Coverification package supports PowerQUICC III
Synthesis tools support radiation-tolerant FPGAs
Analogue/mixed-signal tools run on 64bit Linux
Verification and extraction tools integrated
Software accounts for all sources of signal loss
PCB design tools offer route to RoHS compliance
USB OTG cores meet low-pincount interface specs
Panasonic signs up for high-level synthesis tools
Scan test tool joins reference flow
Siemens signs for global coverage
Peking University picks PCI Express IP
PCI Express IP core runs on Xilinx FPGAs
Volcano acquisition boosts automotive presence
Sanyo opts for algorithmic synthesis
Stretch signs for gigabit MAC IP
EDA forum set for Williams F1 centre
Single-kernel verification engine does the lot
On-The-Go controller makes the mark
Extensions offer powerful solution for ESL design
Mentor commits to support CE-ATA storage
Configurable port meets PCI Express specification
Synthesis tool helps educate FPGA designers
Accellera accepts library donation
PCB systems aided constraint editor system
Assertion synthesis provides the right answer
Bridges link harness design with mechanical CAD
Fraunhofer Institute adopts C synthesis tool
Tool integration makes FPGA design more flexible
Mentor helps with Via reference designs
LSI Logic signs for Ethernet MAC IP
Free seminars explain high level verification
Design environment supports new structured ASICs
Synthesis tools add new Flash FPGA support
Support centres certified worldwide
PCB tools address flex circuit requirements
Design creation tool supports latest re-use specs
Adapters enable system-level verification
Alliance speeds FPGA-on-board designs
Emulator chosen for leading edge Chinese CPU
DFM technology runs on design-to-silicon platform
Millenium signs up for European coverage
Software saves space in FPGA designs
BIST tool tackles embedded memories
Software automates test generation
Verification solution benefits from acquisition
Koenemann brings DFT expertise
StarCore cores gain coverification support
Users group conference calls for papers
IC design deal suits SETsquared startups
Synthesis tools support Virtex-4 FPGAs
Software supports new compact data format
New engines improve nanometre parasitic extraction
Mentor acquires ATA core IP from Palmchip
Upgrade for interconnect design system
Buckley promotes European innovation
Software brings FPGA and PCB design together
Software comes to terms with EDA libraries
64bit Linux systems speed IC design software
Design kit supports SMIC mixed-signal process
Pair to optimise Advanced Switching IP
Parasitic extraction validated for 90nm process
Free software cuts down GDS data
Compiler acquisition to aid dual-core design
Mentor zeroes in on acquisition
Synthesis tool speeds C designs to RTL
New tool speeds Siemens code to RTL
Platform approved for IBM-Chartered process
Simtek adopts parasitic extraction solution
Platform integrated with OpenAccess database
Windows-based PCB system comes up to date
Verification accelerator supports System C
Mentor expands role in IEEE standards
Tools aid automotive and aerospace wiring design
Tools to boost Chinese EDA education
Mixed-signal verification supports HLLs
PCB layout kits are ready for next Intel chipset
Embedded deterministic test speeds to signoff
PCB design tools work together
FPGA platform speeds PCI Express development
Equivalence checker exploits multiple CPUs
Alliance to aid nanometre design
IP library gains verification toolkit
Advantage of integration for Xilinx designers
Faraday uses xRC for parasitic extraction
PCB design software is made for sharing
Award recognises strong web support
Coverification extends to latest ARM cores
Customer support certified again
Full coverage from off-the-shelf PCB design suites
More Chinese penetration for Calibre
Kit simplifies Xilinx multigigabit simulation
Signal integrity analysis at multigigabit speeds
New tool brings complex mixed-signal SoCs together
FPGA software moves to a new level
Mentor acquires Alcatel IP business
Tools to support IBM foundry processes
Software evolves to more complex designs
Support database provides answers online
Tower joins the Calibre fan club
Acquisition boosts packaging expertise
Infineon sorts out nanometre designs
FPGA design flow runs from IP to the PCB
Simulator speeds on latest 64bit platforms
Pair push for embedded Hi-Speed USB
Pair to advance mixed-signal and RF design
Parallel processing speeds nanometre design
Kits support 0.35um mixed-signal process
Silicon Graphics takes shortcut to emulation
Simulator speeds adaptive equaliser to market
Faraday opts for Seamless coverification support
Software stack gets USB controller On-The-Go
Target platform puts IP into hardware emulation
Integrated design and verification for Spartan-3
Mask data preparation supports more formats
IP library gains Hi-Speed USB core
Coverification package analyses system performance
Simulator optimises performance and debugging
SMIC standardises its production
Toshiba to adopt mixed-level IC simulator
Thales takes advice on next-generation products
ATI signs for three-year support deal
Vansco opts for Capital Harness Systems
Higher resolution modelling to boost chip yields
Design rule checking spreads to finer geometries
First complete PCI Express verification solution
Silterra standardises on Calibre
Next-generation emulator for next-generation SoCs
Chinese startup foundry selects Calibre
IP library joins AMI semicustom offerings
Kits speed mixed-signal design
Strong book to bill puts Mentor on track
Web-based IP library suits Faraday
DFT tools speed turnkey SoC services
Programme brings speedy solutions to Siemens
Mentor optimistic about 2003 performance
Seamless coverification support for ARCtangent
IP provides pretested USB 2.0 solution
Mentor and Sharp orchestrate Bach development
IP library gains wireless LAN development platform
PCB design scholarship up for grabs
Programme to expand web-based component info
Third summary judgement of patent infringement
ModelSim achieves Verilog/mixed HDL sign-off
Simulator has high-speed boards covered all ways
Mentor bullish about Q3 showing
Early support for GDSII replacement
Speedy support for Cyclone FPGAs
BIST tool boosts SoC memory reliability
Free seminar looks at PCB and FPGA design
Free EDA training for unemployed engineers
Transistor-level parasitic extraction for SoCs
Front-to-back design flow meets SoC challenges
Simulator focuses on analogue and RF SoCs
FPGAs provide direct verification for ASICs
Software helps in Verilog training course
Coverification speeds race to ARM development
Court rules Cadence infringed Mentor patent
Coverification extends to PowerPC cores in FPGAs
Design kit aims to shrink cellular PCBs
New advantage to multivendor FPGA design flow
Faraday builds in testability with Mentor
Tools set the gold standard for Jazz
Full support package for Axcelerator FPGAs
Mentor closes in on Innoveda acquisition
Web-based access to revision-controlled IP library
HDL simulation works on Fujitsu ASICs
TSMC supports Mentor design rule checking
Motorola adopts FormalPro for basestation ASICs
Suite ARMs designers for embedded development
Progress for Mentor in Innoveda acquisition
New-generation emulator tackles more complexity
Deal provides improved verification
Multicore debugging boosts Symbian deployment
Hum and Selosse step up at Mentor
Ricoh adopts Mentor Graphics LBISTArchitect
Interface-based design simplifies IC interconnects
Synthesis demo by video-on-demand
Design flow speeds programmable SoC solutions
US court rules for Mentor: Cadence case continues
Upgraded synthesis for programmable logic devices
Design-for-test tool successfully run on ARM core
Library boosts PCB design software
Improved debugging for simulator
LSI Logic signs off Mentor's ModelSim
Mentor to acquire IKOS after Synopsys drops out
Altera bases SoPC development on Mentor models
Mentor takes over Accelerated Technology
Data preparation software aids mask accuracy
Design tool support extends to latest FPGAs
STMicroelectronics signs off ModelSim
Platform ready for future programmable SoCs
Capital ideas in next-generation harness design
Busy time for Mentor at SPIE conference
Enhancement speeds prototyping and verification
FPGA prototyping speeds SoC verification
STMicroelectronics adopts Mentor's IBIS
Oki standardises on Calibre for fine geometries
Calibre ranks higher for Mentor
Record fourth quarter for Mentor
Productivity gains claimed for updated PCB suite
Derrick takes Mentor to market
OnLine knowledge centre for web-based EDA training
Mentor expects improved earnings in Q4
Easier route to core IP library
Packs keep design software up to date
Alcatel Canada standardises on Mentor Celaro
USB macrocell combines both the latest flavours
IP library gains top Gigabit Ethernet MACs
FPGA software imports legacy designs with ease
Physical verification extended to SiGe process
Mentor improves on pessimistic Q3 forecast
IP cores add network functions to PLDs
Mentor joins Open System C Initiative
Parthus takes USB function controller from Mentor
Mentor has designs on student bodies
HTML documentation is net gain for design suite
Windele takes charge of Europe for Mentor
Verification extends to mask making
Adelante helps Mentor address DSP-based SoCs
Hitachi signs-off ModelSim simulator
Design for test method cuts ATE overheads
Simulation extends to debug and design analysis
Power plane analysis joins high-speed toolkit
Mentor joins Common Licence Consortium
Mentor certifies three technology providers
Coverification support for 32bit media processor
FPGA synthesis stretches to millions of gates
Advanced routing added to PCB design tools
Soft IP puts key functions on PLDs
IP reference solution for USB 2.0 peripherals
Platform accelerates SoC design and verification
Design data management takes in supply chain data
Equivalence checker goes multilingual
Kit aids 0.18-micron mixed-signal design
SoC system optimised for knowledge management
System verifies effective use of IP
Half of all European electronic products ship late
Mentor first with support for new MIPS processor
Pattern optimisation enhances ATPG tool
STMicroelectronics standardises on Mentor
Cell, block and full-chip verification in one
Mentor launches emulation services worldwide
Co-verification support for PowerPC architecture
Mentor holds Scotland and Ireland Designer Forum
Nordic comes to Mentor for SoC verification
Mentor and Altera to push Excalibur
VRTX puts MIPS32-based SoC designs in real time
Siroyan bases its debugger on Mentor's XRAY
STMicroelectronics goes for subwavelength Calibre
Program makes better use of IP in FPGAs
Advanced design technology added to PCB design
Board timing analysis tool upgraded
Data exchange smooths subwavelength IC design
Mentor upgrades wiring harness design suite
Mentor and Xilinx have cores for communications
Mentor supports TI DSPs and MCUs
Mentor Graphics and UMC deliver IC design kits
