Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Tau 2.3
Edited by the Electronicstalk Editorial
Team on 15 March 2001
Board timing analysis tool upgraded
Mentor Graphics and Altera have jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis.
Mentor Graphics and Altera have jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis Mentor Graphics has also announced the availability of the Tau version 2.3 tool
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Tau is the only timing analysis tool developed specifically for board verification.
Tau 2.3 offers enhanced usability through additional analysis feedback features with continued support for PLDs with the STAMP interface format.
The need for common data formats between PLD and PCB designers is driven by the continued increase in the use of complex, high-speed PLDs, especially in the networking and communications industries in which time-to-market is particularly critical.
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In addition, as the complexity and speed of both PLDs and PCBs continues to increase, quick, accurate board-level timing analysis allowed by the standard timing data interface is essential.
Altera has added STAMP interface support to the latest version of its PLD design toolset, QuartusT II development software.
The Quartus II development software will now output component timing information in the STAMP standard format, part of the LibertyT open source library format from Synopsys, which can be used by Tau, Mentor's board-level timing analysis tool, to quickly create Tau timing models.
"With high-density, high-speed PLDs at the core of many of today's system designs, verifying board-level timing is critical to ensuring reliable system operation early in the design cycle", said Henry Potts, general manager and vice president, Systems Design Division, Mentor Graphics.
"This joint effort with Altera will clearly benefit our mutual customers with a common data interface for timing analysis and verification".
"Our new products are pushing the performance envelope.
The new Mercury programmable ASSP device family offers data rates of up to 1.25Gbit/s and a total CDR bandwidth of up to 45Gbit/s which makes board level verification critical", said Tim Colleran, Altera vice president of product marketing.
"By allowing easy data transfer between Altera's Quartus II development software and Mentor's Tau product, we can really enhance the design verification process".
Mentor heralds Tau as the industry's only comprehensive board-level timing analysis solution.
It uses symbolic timing analysis to automatically eliminate reporting of false timing problems that can occur when traditional static timing analysis tools are used at the board level.
Tau 2.3 includes several new features designed to make the tool easier to use.
The latest version offers an enhanced user interface for model selection, compilation, and block diagram viewing with greater interoperability support.
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