Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 12 April 2001
Mentor and Altera to push Excalibur
Mentor Graphics and Altera have unveiled a strategy to deliver a complete "front-to-back" design methodology for Altera's Excalibur system-on-a-programmable-chip (SoPC) technology.
Mentor Graphics and Altera have unveiled a strategy to deliver a complete "front-to-back" design methodology for customers using Altera's Excalibur system-on-a-programmable-chip (SoPC) technology Excalibur solutions feature the implementation of embedded processors that were previously only available with traditional ASIC design methodology
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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The first solution in this initiative is the introduction of customised coverification processor support packages (PSPs) for Altera's ARM-based Excalibur embedded processor solutions.
The custom PSP is based on the cycle-accurate PSPs for ARM-based Excalibur solutions already available in Mentor's Seamless coverification environment (CVET) model library.
With Seamless CVE and the PSPs for ARM-based Excalibur solutions, Altera customers can verify the embedded cores within Excalibur devices and the external interfaces to off-chip components during their design and debug phases, shortening overall design cycles by increasing the chance of first pass success.
The complete design solution will include EDA tools for design capture, simulation, hardware/software coverification, embedded software, physical synthesis, board-level signal integrity and C-based high-level design, in addition to embedded IP MegaCore logic functions.
These new tools will provide early visibility into the design and verification process and will enable design teams to make tradeoffs throughout the design cycle that will increase their ability to reach time-to-market, performance and feature requirements.
The new availability of co-verification support adds to recent Altera Excalibur solutions support announcements from Mentor Graphics.
On 12th March 2001, Mentor Graphics and Altera announced support for the STAMP timing file format, allowing PLD and printed circuit board (PCB) designers to easily share PLD timing data for efficient board-level timing analysis.
In addition, Altera already has OEM agreements with Mentor Graphics for its LeonardoSpectrum synthesis and ModelSim simulation tools.
Altera has integrated both tools into its Quartus II and MAX+PLUS II development environments, and offers these to customers as part of its standard annual subscription agreement.
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