Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre Interactive
Edited by the Electronicstalk Editorial
Team on 06 June 2001
Cell, block and full-chip verification
in one
New from Mentor Graphics, Calibre Interactive enables designers to perform block and cell physical verification from within layout environments such as Cadence Virtuoso.
New from Mentor Graphics, Calibre Interactive enables designers to perform block and cell physical verification from within layout environments such as Cadence Design Systems' Virtuoso This provides the same integrated cell, block and full chip verification environment to Virtuoso users that has existed for the IC Station tool users for years
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Accessible directly from the layout environment, Calibre Interactive brings unprecedented performance, capacity, functionality and ease-of-use to block/cell physical verification.
It provides the block/cell designer interactive access to design rule checking (DRC) and layout versus schematic (LVS) checking and the ability to graphically debug verification results without leaving the layout environment.
Designers invoke all three of these capabilities via a graphical user interface called directly from the layout tool's pull-down menus.
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Users designing analog circuitry and smaller cells and blocks where interactive verification is a requirement can easily adopt this methodology.
"Historically, Calibre provided our customers with a competitive advantage during tape-out through superior performance, capacity and ease-of-use", said Joseph Sawicki, general manager for the Calibre Business Unit.
"The introduction of Calibre Interactive now allows our customers to deploy the power of Calibre for cell and block verification, and also gain the advantages of using a single, industry-standard, verification tool suite throughout their design cycle".
Using the Calibre tool suite throughout the flow facilitates design integration and reduces design cycle time.
With SoC design becoming more pervasive in the industry, most new designs incorporate a variety of full-custom, place and route, analog, memory, and mixed-signal design on a single chip.
The Calibre toolset's design style independence enables it to efficiently verify any design without user intervention to optimise the rule file for different design styles.
Design cycle time reductions arise from three sources.
First, Calibre Interactive is fully compatible with Calibre, allowing Calibre customers to make use of their already extensive inventories of full-chip rule files for block/cell verification.
In addition, block/cell designers can now employ the extensive set of Calibre rules provided by Mentor's foundry partners, including Chartered Semiconductor Manufacturing, IBM, TSMC and UMC.
Second, using Calibre as their single verification tool suite for block/cell and full-chip tape-out allows Calibre customers to avoid the physical verification discrepancies that arise when different verification flows are used at multiple design stages.
Customers save valuable time during full-chip tape-out, since physical verification errors within blocks are now manifested and corrected early in the design process.
Finally, CAD teams using Calibre Interactive now have only a single verification flow to maintain and deploy.
This not only saves the time of scarce CAD experts; it also reduces training requirements for the team and ultimately enables a deeper level of tool expertise.
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