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Design and Development Software
News Release from: Mentor Graphics UK | Subject: FastScan 2001.2
Edited by the Electronicstalk Editorial
Team on 13 June 2001
Pattern optimisation enhances ATPG tool
FastScan 2001.2 is the latest version of the automatic test pattern generation (ATPG) tool from Mentor Graphics for improving test coverage in ASIC, IC and SoC designs.
FastScan 2001.2 is the latest version of the automatic test pattern generation (ATPG) tool from Mentor Graphics for improving test coverage in ASIC, IC and SoC designs FastScan 2001.2 offers new and enhanced features for increasing productivity and overall test quality, including a new pattern optimisation solution and improved "at-speed" test generation functionality
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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The new version of FastScan greatly enhances the designer's ability to reduce time-to-market and test costs while ensuring maximum test coverage.
Unique to the design-for-test (DFT) industry, FastScan 2001.2 now provides pattern optimisation capabilities for ensuring that final test patterns are ordered from the most effective to least effective.
Pattern optimisation guarantees that if a test set must be truncated due to automatic test equipment (ATE) limitations, maximum test coverage is preserved.
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By delivering the most effective patterns up-front, FastScan 2001.2 also reduces the test time required for failing devices, reducing the overall test cost.
"We have a number of customer ASICs with very large scan pattern sets, even when using all the compression features in FastScan", said Ken Butler from the ASIC Test Group of Texas Instruments.
"We asked Mentor to implement a pattern ordering feature and are encouraging our customers to use it when generating their ATPG patterns.
If test sets are truncated, such as for burn-in or other tester memory-limited situations, we can ensure a higher fault coverage.
Test cost is also minimised since failing devices will tend to exit the tester program earlier than they would without this feature".
As feature sizes of today's VLSI devices continue to shrink and as clock speeds continue to multiply, at-speed testing is becoming a more critical piece of the overall DFT strategy.
The use of functional patterns for at-speed testing is becoming cost prohibitive and yields questionable fault coverage.
Through a collaborative effort with Motorola, Mentor has enhanced FastScan's at-speed test generation solution to keep pace with these growing requirements.
Already a proven at-speed test solution within the industry, the new enhancements further improve test quality and reduce the designers' reliance on functional at-speed testing.
"We've been working closely with Mentor's DFT division during the past year to ensure FastScan's at-speed solution handles our most demanding designs," stated Raj Raina, manager of PowerPC Design-for-Testability, Motorola's Semiconductor Products Sector.
"Using the latest at-speed capabilities of FastScan, we have improved scan-based transition fault coverage by up to 22 percent on a 500MHz, 10.5 million gate microprocessor design.
FastScan's latest capabilities also appear to significantly reduce the manual effort needed to debug at-speed testability issues.
We look forward to continuing this collaborative effort with Mentor DFT as the need for scan-based at-speed testing becomes even more crucial to our overall DFT strategy".
FastScan 2001.2 is now available through Mentor Graphics.
Pattern optimisation capabilities are included as part of the base product and at-speed test generation solutions start at US $25,000.
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