Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 15 June 2001
Half of all European electronic products
ship late
Half of all European electronic products ship late and a quarter of European electronic designs hit the market with known bugs, according to a survey funded by EDA vendors
and a quarter of European electronic designs hit the market with known bugs These are the stark findings of an independent survey of 231 managers and engineers in electronics engineering companies across the UK, France, Germany and Scandinavia completed by Enterprise Planning and Research (EPR) in the second quarter of 2001
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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76% of respondents said that because their project deadlines were usually too tight to permit thorough design verification they were forced either to ship late or to ship with known bugs.
50% percent break their deadlines in favour of doing more verification.
Rather than ship late, 26% send their products out knowing that they contain bugs.
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Mentor Graphics contributed questions on verification to the EPR survey, which it funded jointly with other major EDA vendors, on the basis that it would have exclusive access to the results.
The company has today released these findings.
Comments Karsten Popp, President of Mentor Graphics Europe: "Top executives at electronics companies don't seem to be aware of the risks being taken with their brands by releasing buggy products to market or of the precise impact of inadequate verification on their margins due to late shipment.
With new tools and chip capacities engineers are creating designs that are harder to verify than they are to design.
The hardest problem is verifying something through millions of possible scenarios to make sure it will do what the customer expects.
Verification is undoubtedly the most serious bottleneck today - typically it takes 50-70% of the design time - and the vast majority of companies are being severely hurt by outdated verification strategies".
Only 15% of respondents said that the project deadlines they were given for designing electronic products were usually sufficient to permit thorough design verification.
Executives cannot comfortably shrug off these findings by saying that the bugs that get through are trivial.
The survey asked a question specifically about the causes of severe bugs: incomplete system verification was substantially the most commonly cited cause.
Popp continues: "Smart verification strategies don't have to take longer or force you to hire more designers.
There are newer technologies available to solve the system verification problem such as virtual prototyping using hardware emulators, equivalence checking or hardware/software coverification and embedded software tools.
The key is to move system verification earlier into the design process thereby shortening the design cycle".
The survey covered a broad range of respondents working on PCB, ASIC, FFPGA, full custom IC and system-on-chip designs.
Half of the respondents were design engineers and most of the remainder engineering management.
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