Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: TestKompress
Edited by the Electronicstalk Editorial
Team on 03 October 2001
Design for test method cuts ATE
overheads
Mentor Graphics has developed a new patent-pending design-for-test technology that it reckons extends the capacity of ATE for a significant reduction in the cost of semiconductor testing.
Mentor Graphics has developed a new patent-pending design-for-test (DFT) technology called Embedded Deterministic Test (EDT) that it reckons extends the capacity of automatic test equipment for a significant reduction in the cost of semiconductor testing, which can represent as much as 50% of manufacturing costs Mentor's first EDT product, TestKompress, employs the new compression technology that allows semiconductor manufacturers to reduce the ATE memory and time requirements for testing ASIC, IC and SoC designs by up to 10 times
This article was originally published on Electronicstalk on 2 Feb 2004 at 8.00am (UK)
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Motorola used the TestKompress embedded deterministic test tool for the manufacturing test of its new MRC6011 reconfigurable compute fabric device.
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Mentor Graphics has added new automated functionality to its FastScan automatic test pattern generation tool and its TestKompress embedded deterministic test tool.
This reduction allows manufacturers to maximise the usage of state-of-the-art test equipment without jeopardising product quality and to reduce the cost of future ATE purchases.
According to Prime Research Group, the semiconductor industry spent $4.9 billion in 2000 on digital IC and SoC tester purchases.
At least 60% ($2.9 billion) of this investment was made to meet the increased capacity requirements.
Further reading
Compression software improves ATPG
TestKompress 2007 is an enhanced version of the ground-breaking tool from Mentor Graphics that introduced scan test pattern compression to the marketplace.
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
The shift from 200 to 300mm wafers by most leading manufacturers and the use of new fault models to detect failure mechanisms associated with deep submicron (DSM) designs are expected to continue to drive the need for additional test capacity.
"While the cost of semiconductor manufacturing continues to drop sharply year after year, the cost of test has continued to rise due to skyrocketing gate count, increasing complexity, larger wafer size and changing process technology", said Walden C Rhines, chairman and CEO of Mentor Graphics.
"From a purely economic standpoint, the impact that EDT technology will have on the semiconductor manufacturers in terms of reduction in capital spending could make TestKompress one of the most important product introductions by Mentor".
By increasing the capacity of test equipment, manufacturers are not required to purchase expensive ATE memory upgrades or use test pattern reloads or multiple pass testing.
Test data compression results from the combination of embedding test logic and the new deterministic test pattern generation algorithms.
The test logic is embedded at the interface between the scan chains and the tester pins without changing the system logic.
In addition, the tight coupling of test logic and test pattern generation eliminates the need for test point insertions and X-bounding logic used with other DFT methods.
The volume of devices that can be tested in a manufacturing facility is determined by the amount of test time available.
Currently scan testing is the largest and most rapidly growing obstacle to production throughput and can often represent more than half the total test time.
TestKompress solves this issue by reducing the scan test by up to 10 times, which increases the volume of devices tested per ATE by up to 80%.
"TestKompress reduced the test data volume by 10 times in our evaluation and it may eliminate the need to increase ATE memory for the next several years", said Yoshio Okamura, Department Manager, Design Technology Development Division, Semiconductor and Integrated Circuits, Hitachi.
"In addition the scan test time was significantly reduced".
TestKompress is fully compatible with time-proven scan and automatic test pattern generation (ATPG) design-for-test flows.
TestKompress uses the same scan DFT methods, script files and ATPG libraries as Mentor's FastScanM product.
The solution also supports all scan methodologies and fault models.
Additionally, TestKompress uses the same test vector formats and tester interfaces enabling seamless and intuitive ATE integration and adoption for users.
The TestKompress product is immediately available in two versions: The TestKompress 5X product provides users with compression benefits up to five times and TestKompress 10X reduces the test data and test time by up to 10 times.
Both products are available under term licences with pricing beginning at approximately $2 million.
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