Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: FPGA Advantage 5.2
Edited by the Electronicstalk Editorial
Team on 14 November 2001
FPGA software imports legacy designs
with ease
FPGA Advantage 5.2 from Mentor Graphics provides designers with an integrated environment for design creation, management, simulation and synthesis of FPGAs.
FPGA Advantage 5.2 is the latest version of the HDL design flow package from Mentor Graphics that provides designers with an integrated environment for design creation, management, simulation and synthesis of FPGAs FPGA Advantage 5.2 delivers new documentation features that improve design creation and design reuse, and synthesis enhancements that generate more accurate timing data
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Enhancements across the entire flow provide designers with a smoother and more robust design solution that simplifies the creation of complex FPGAs and programmable logic devices.
"FPGA Advantage 5.2 includes our most robust feature-set to date, including best-in-class features for design documentation and creation, and incremental synthesis for complex designs", said Valerie Rachko, director of marketing for FPGA Advantage.
"With this release, we achieved smoother integration between stages in the flow, enabling designers to move seamlessly between design creation, synthesis and simulation at the push of a button".
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A common bottleneck in design reuse has been the time expended importing legacy code into a new design.
FPGA Advantage 5.2 includes a new recursive file search feature that allows designers to quickly set up and search through a directory of IP files to import a complex design.
Designers can view the reused design's structure prior to design inclusion, enabling smoother integration of legacy code.
FPGA Advantage 5.2 also includes new HTML documentation that allows companies to share designs across a secure website.
The designs are presented in an easy-to-understand format that shows both design hierarchy and the relationships between different hardware descriptions.
Improvements have also been made to the HDL2Graphics conversion engine in FPGA Advantage 5.2.
The new version includes support for incremental code recovery.
When incremental changes are made in text, FPGA Advantage 5.2 makes it easy to identify where the change was made in the corresponding graphical view.
Mentor's newly patented Interface-Based Design (IBD) technology allows designers to simplify interconnect creation problems by displaying design interconnect structures in an easy-to-view and compact tabular format.
FPGA Advantage 5.2 includes new global signal and comment columns that improve the readability of generated HDL code, enabling designers to easily tag selected elements of a design.
Improvements to IBD have also streamlined the downstream synthesis flow.
Designers can now set synthesis attributes on any net, port, block and component and have these attributes transferred automatically to the synthesis engine.
FPGA Advantage 5.2 now extends support of the Mentor Graphics TimeCloser synthesis technology to Altera, with Altera's Quartus-II design environment.
The TimeCloser technology enables designers to optimize true critical paths based on the physical data generated by the place and route tool.
With advanced optimisation techniques to generate the synthesis timing results to drive place and route, the overall device performance is improved, helping designers achieve better timing results with minimum iterations.
FPGA Advantage 5.2 is available immediately through Mentor Graphics' multitiered distribution network.
All versions of FPGA Advantage 5.2 support all major FPGA vendors.
Customers have the ability to choose from an entry-level FPGA design flow solution designed for the single FPGA designer, starting at $12,000, to a complex FPGA design flow solution for workgroups starting at $45,000.
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