Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: LBISTArchitect
Edited by the Electronicstalk Editorial
Team on 11 April 2002
Design-for-test tool successfully run on
ARM core
The LBISTArchitect tool from Mentor Graphics has been successfully used to implement logic built-in self test (BIST) for the ARM966E-S microprocessor core.
The LBISTArchitect tool from Mentor Graphics has been successfully used to implement logic built-in self test (BIST) for the ARM966E-S microprocessor core Mentor's LBISTArchitect tool aids in reducing test costs by adding a small test controller that self-tests embedded cores or ICs
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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BIST tests a chip's circuits without using external patterns, effectively resulting in a chip that can test itself.
Logic BIST was successfully implemented on the ARM966E-S core using LBISTArchitect.
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The ARM966E-S processor is a full scan core with test coverage that exceeds 99% with ATPG.
The Design-for-Test (DFT) group at ARM found the LBISTArchitect tool and methodology easy to use for implementing BIST.
ARM established that the silicon area needed to be dedicated to Logic BIST itself was less than 5% of the total area of the core and that test coverage for the microprocessor core was in excess of 95%.
"We are pleased to have this opportunity to work with an industry leader such as ARM.
Mentor's LBISTArchitect delivered the ease of use and high test coverage ARM needed when they implemented BIST and verified their synthesisable ARM966E-S core", said Stephen Shostek, Logic BIST Business Unit Manager, Mentor Graphics.
"Logic BIST plays a central role in enabling test-ready intellectual property (IP) since the test can be built in from the beginning.
Developers of system-on-chip devices are under increasing pressure to keep physical characteristics, such as die size and power consumption to a minimum.
This pressure creates an increasing demand for more efficient and easy to use DFT tools such as LBISTArchitect".
"ARM continues to evaluate test methodologies to accommodate our Partners' present and future test needs.
The successful implementation of the Mentor LBISTArchitect tool on the ARM966E-S core adds another possible solution for ARM partners with SoC hierarchical capabilities", said Teresa McLaurin, Design for Test manager, ARM.
Mentor's LBISTArchitect is a complete DFT product for implementing logic BIST in a design.
The product contains patented BIST-Ready technology that ensures fault coverage comparable with leading-edge automatic test pattern generation (ATPG) tools without the timing, routing and power dissipation overheads traditionally seen in BIST.
LBISTArchitect's design rules checks can be run at any stage of the design and test process, and combined with the parameterisable BIST controller, ensure that the test and BIST implementation can handle engineering change orders (ECOs) without the need for resynthesis.
LBISTArchitect can be completely integrated with the Mentor Graphics FastScan ATPG and BSDArchitect New Edition boundary scan synthesis products for a complete DFT solution.
ARM carried out this project to determine the feasibility of implementing Logic BIST on its sythesisable cores using commercially available tools.
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