Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Atmel
Edited by the Electronicstalk Editorial
Team on 12 April 2002
Design flow speeds programmable SoC
solutions
Mentor Graphics and Atmel have developed a comprehensive design flow for Atmel's award winning programmable SoC solutions.
Mentor Graphics and Atmel have developed a comprehensive design flow for Atmel's award winning programmable SoC solutions, enabling embedded system designers to significantly increase productivity and accelerate time-to-market Under a new agreement, Atmel will license three premier tools from Mentor Graphics, including customised versions of the Seamless coverification environment, the ModelSim HDL simulator and LeonardoSpectrum synthesis tools
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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The result is a unified environment for the codevelopment and coverification of both the integrated AVR processor code and the HDL hardware design FPGA portions of programmable SoCs.
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The System Designer design and coverification environment that results from the integration of the Mentor and Atmel tools allows the FPGA's HDL design to be verified concurrently with the debugging of the MCU code.
The designer has full visibility into the processor's program counter, memory, registers and peripherals and into the performance of the FPGA, at every stage during the HDL simulation.
"Mentor Graphics is the only EDA company that has addressed and solved the issue of designing and verifying programmable SoC devices.
No other EDA vendor has as comprehensive and integrated a solution", said Joel Rosenberg, director of PSLI products for Atmel.
"Our System Designer tool suite provides the only comprehensive design solution for programmable SoCs.
We could not have created our design flow without Mentor Graphics".
"Our sustained partnership with Atmel demonstrates Mentor's commitment to providing comprehensive system-level solutions for all FPGA-based products and specifically for programmable SoCs", said Anne Sanquini, vice president and general manager of the HDL Design division, Mentor Graphics.
"Atmel continues to push the limits of programmable system-level integration and Mentor's tools continue to support its latest innovations, while at the same time minimising design risk and reducing design cycles".
Seamless allows users to validate hardware/software interfaces in a virtual and unified environment.
Coverification provides a high-visibility design debug environment enabling the early detection and correction of potential software code and/or hardware logic errors.
Tailored to the FPSLIC architecture, Seamless is designed to address the coverification needs of Atmel's customers.
The Seamless tool uses pre-existing knowledge of the embedded processor and memory system to eliminate the configuration stage traditionally associated with coverification tools, making coverification a push-button process in the System Designer tool suite.
The Mentor Graphics ModelSim HDL simulator tool is aimed at today's multi-million gate ASIC and FPGA designs.
The need to detect errors in the development cycle, before synthesis and place and route, becomes increasingly important in improving engineering productivity.
ModelSim provides FPSLIC designers access to a complete VHDL or Verilog-based design flow, including RTL and gate-level HDL simulation and synthesis.
The Mentor Graphics LeonardoSpectrum synthesis tool allows Atmel users to create FPGA designs in VHDL or Verilog using one synthesis environment.
LeonardoSpectrum eases the creation and management of FPSLIC designs used in markets such as industrial control, communications, broadband, wireless and multimedia.
Combining push-button ease-of-use features and sophisticated design strategies, LeonardoSpectrum allows Atmel designers to carefully control and optimise FPGA designs to meet their exact design requirements.
In addition to the Mentor Graphics and AVR Studio development tools, Atmel's System Designer has an HDL Planner module that allows firmware developers who are not familiar with hardware description languages to rapidly create syntactically correct Verilog or VHDL designs for the embedded FPGA logic inside FPSLIC.
Using a top down design flow, the designer creates hardware components using any of more than 50 point-and-click macro generators.
In addition, HDL Planner will automatically generate architecturally optimised layout and post layout Verilog or VHDL models for the FPGA portion of the design.
Available today, Atmel's ATSTK94 FPSLIC starter kit contains a four-month software license and an FPSLIC prototyping hardware kit for $495.
System Designer version 2.0 is available now for $995 for an annual subscription, or $2495 for a perpetual license.
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