Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 10 July 2002
Faraday builds in testability with
Mentor
Faraday Technology Corp has selected Mentor Graphics design-for-test (DFT) tools for its SoC design flows.
Faraday Technology Corp has selected Mentor Graphics design-for-test (DFT) tools for its SoC design flows Faraday selected Mentor Graphics for its proven DFT technology and ability to improve productivity and test quality and reduce test cost
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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As a leading supplier of silicon-proven intellectual property and a leading provider of SoC design services, Faraday recognises today's SoC designs require multiple test solutions to guarantee thorough testing of these devices.
Mentor Graphics offers the industry's most complete portfolio of DFT tools for testing complex SoC designs.
These tools provide high fault coverage as well as the flexibility to fit into any design flow.
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Faraday will use the FastScan tool for automatic test pattern generation (ATPG) and the MBISTArchitect tool for memory built-in self-test (BIST).
To complete its test flow, Faraday also adopted the BSDArchitect tool for automated boundary scan implementation, the DFTAdvisor tool for scan synthesis and testability analysis and the DFTInsight tool for graphical DFT debug and analysis.
"We work on very aggressive development schedules with limited bandwidth", said Dr George Huang, vice president of ASIC Technology for Faraday Technology.
"Mentor Graphics offers the DFT products we need to generate very high quality tests for our SoC designs in the least amount of time".
Faraday was impressed with the MBISTArchitect tool's comprehensive array of memory BIST features designed to save chip area and achieve high fault coverage with minimal test time.
Faraday can select from a set of pre-defined industry-standard algorithms, such as March C and checkerboard, or the tool's own MBIST Flex user-definable algorithm which applies at-speed tests with flexible pattern applications to detect technology specific defects.
The MBIST Full-Speed feature, an at-speed BIST capability with pipelining techniques, significantly reduces test application times while the tool's comprehensive configurations facilitate high test set reusability.
FastScan provides Faraday with leading ATPG technology, an intuitive interface and a range of fault models.
The tool also offers advanced fault analysis techniques, comprehensive design rule checking, pattern compression and optimisation capabilities, industry-proven at-speed test generation functionality and delivery of the highest coverage test sets for their ASIC and SoC designs.
"The breadth of Mentor DFT solutions offer customers such as Faraday a comprehensive test solution for today's most complex SoC devices", said Robert Hum, vice president and general manager, Model Technology group and Design-for-Test group, Mentor Graphics.
"Our leadership in the DFT industry ensures that as technologies evolve, Mentor will be ready with solutions that continue to improve test quality and reduce test costs".
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