New advantage to multivendor FPGA design flow

FPGA Advantage 5.3 is the latest version of the industry-leading HDL design flow for managing the creation, simulation and synthesis of field-programmable gate array devices.

FPGA Advantage 5.3 is the latest version of the industry-leading HDL design flow for managing the creation, simulation and synthesis of field-programmable gate array devices.

FPGA Advantage 5.3 adds new design management features, including enhanced Interface-Based Design (IBD) support and advanced debugging features, which simplify and ease the design of multi-million-gate FPGAs.

"Titan Aerospace Electronics is committed to developing next-generation FPGA designs that push current technological limits", said Robert Jacobson, principal engineer, Titan Aerospace Electronics.

"Mentor's FPGA Advantage 5.3 tool allows design teams to design, manage, debug, simulate and synthesise our complex FPGA designs quickly and effectively.

With this all-in-one tool, Mentor Graphics continues to raise the bar in developing state-of-the-art FPGA design solutions".

The FPGA Advantage 5.3 IBD editor solves problems design engineers have with complex interconnect creation.

IBD allows complex interconnect structures to be viewed in a compact tabular format.

Users can rapidly specify the signal connections and automatically generate the equivalent structural description in VHDL or Verilog.

The IBD tabular format also enables design constraints and synthesis properties to be specified and then be propagated to the downstream phases of the design flow.

FPGA Advantage's debugging capabilities have been expanded with version 5.3 to include visualisation of text files during interactive simulation debug.

These graphical and tabular diagrams of HDL source code enhance HDL simulation and improve design verification productivity.

FPGA Advantage 5.3 provides additional enhancements for FPGA designers, including: the ability to add and remove hierarchy levels; frames for multiple instance instantiations; signal stubs for signal slicing; dataflow window X-tracing; and support for Microsoft Windows XP "Mentor Graphics continues to extend FPGA Advantage's capabilities to handle the latest device complexities from the FPGA market leaders", said Valerie Rachko, director of marketing, HDL design and FPGA solutions, Mentor Graphics.

"Mentor is the only EDA tool vendor to offer an integrated FPGA design flow for design creation, debug, simulation and synthesis".

FPGA Advantage 5.3 adds Verilog support for Altera Corp's MegaWizard Verilog plug-in manager and LogicLock.

The MegaWizard plug-in manager allows a designer to customise megafunctions in either VHDL or Verilog without changing the design's source code.

LogicLock enables hierarchical and incremental design within the Altera Quartus II design environment.

FPGA Advantage 5.3 continues to offer VHDL and Verilog support for Xilinx Core Generator, allowing designers to incorporate large blocks of IP directly and seamlessly into the design flow for Xilinx devices.

FPGA Advantage 5.3 is available immediately through the Mentor Graphics unique multitiered distribution network.

All versions of FPGA Advantage 5.3 support all major FPGA vendors.

Customers have the ability to choose from an entry-level FPGA design flow solution designed for the single FPGA designer, starting at $12,000, to a complex FPGA design flow solution for workgroups starting at $45,000.

(This was Electronicstalk's Top Story on 11 July 2002).

Back to top