DFT tools speed turnkey SoC services

Goyatek Technology (Goya) has standardised on Mentor design-for-test (DFT) tools for its DFT service flow.

Goyatek Technology (Goya) has standardised on Mentor design-for-test (DFT) tools for its DFT service flow.

Mentor's MBIST Architect memory built-in self-test (BIST) tool and BSD Architect boundary scan automation tool were selected for their technology leadership and for ongoing improvement of Goya's DFT capabilities.

Goya is a provider of Taiwan Semiconductor Manufacturing Company (TSMC)-based SoC/ASIC turnkey services and intellectual property (IP) and is known for its outstanding engineering capabilities supporting TSMC's advanced process technology.

Goya is the first TSMC design services partner to support and complete both 180 and 250nm designs.

Because of its work with these complex design process technologies, coupled with the varied design flows used by its customers, Goya requires DFT tools that provide superior test coverage, flexibility and innovative at-speed testing capabilities to ensure high test and, ultimately, end-product quality.

"Our work with complex design processes as well as IP requires that we use the most advanced tools and test techniques available", said Nai-Yin Sung, CAD Director of Goya.

"Mentor Graphics offers the best DFT tools in the industry and fit into any design flow, which is important to us and to our customers.

The MBIST Architect and BSD Architect tools offer us a comprehensive selection of features that save us time and provide the highest test quality available".

The MBIST Full-Speed feature within the MBIST Architect tool accelerates traditional "at-speed" testing by applying a patent-pending pipelining technique to simultaneously apply patterns, read them back and compare the results.

This process significantly reduces test application times, facilitates high test-set reusability and produces high-quality tests.

The BSD Architect tool dramatically reduces development time by automating the implementation of boundary scan circuitry.

The tool's flexible test access port (TAP) synthesis engine supports any boundary scan configuration to thoroughly test internal structures such as memory BIST, embedded cores and IP.

"As our customers face more complex design challenges we need to be ready with advanced test solutions that can be used now", said Robert Hum, Vice President and General Manager, Design Verification and Test group, Mentor Graphics.

"The move to nanometer processes introduce problems that are difficult to detect and can have a tremendous impact on yield.

By enhancing capabilities such as at-speed test we are able to equip our customers with a competitive advantage".

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