Higher resolution modelling to boost chip yields

The latest significant enhancements to the Calibre suite of resolution enhancement technology (RET) tools effectively ensure Calibre's RET modelling accuracy for the next three technology nodes.

Mentor reckons that the latest significant enhancements to the Calibre suite of resolution enhancement technology (RET) tools will effectively ensure Calibre's RET modelling accuracy for the next three technology nodes.

These enhancements deliver substantial improvements in the accurate modelling of the application of RET in sub-100nm IC manufacturing processes, and are imperative in the effort to increase customer profitability by improving chip yield and time-to-silicon, especially for the demanding 65nm technology node and beyond.

As IC manufacturers grapple with subwavelength feature sizes, extreme pressure is placed on the complex lithographic system that patterns circuits on silicon.

RET modelling accuracy becomes increasingly important in the sub-100nm nodes where the process window (parameters at which the process delivers yielding silicon) shrinks dramatically.

Accurate RET modelling of the complex lithographic system is pivotal in ensuring pattern fidelity despite the distortions that occur in sub-100nm generations, where critical IC features are one-third the wavelength of the exposure equipment.

Before full-chip RET operations, there are a number of key model calibration and creation steps.

During model setup, the user inputs key parameters such as test pattern silicon measurements, exposure wavelength, numerical aperture (NA), sigma and the illumination pattern.

The enhancements announced today, Calibre VT5 (Variable Threshold - version 5) and TCCcalc (vector, thin-film optical calculations) are major extensions to the Calibre RET silicon modelling and OPC technology base.

The resulting new TCCcalc optical model is fitted to the data, with resist and etch effects handled by the new VT5 model.

The model's predictive ability is verified versus silicon, then used by VT5 in conjunction with batch, full-chip RET software for production.

VT5 and TCCcalc are the result of more than 18 months of engineering, as well as beta testing in the world's leading 90 and 65nm R and D fabs.

They include support for ultra-high-NA (numerical aperture) optical effects as well as multi-exposure RET methods and irregular resist/etch effects.

In addition, there are a number of other deep subwavelength enhancements to the Calibre RET tools, including custom illumination support and image optimisation algorithms, that, when combined with VT5 and TCCcalc, provide world-class RET accuracy for the rest of the decade.

"AMD has used Mentor Graphics Calibre RET products since their introduction in 1999.

The combination of powerful hierarchical design rule checking (DRC) software with physically based optical and process correction (OPC) models allows us to develop customised and accurate solutions to meet our OPC requirements", said Chris Spence, AMD.

"The VT5 and TCCcalc capabilities improve the OPC accuracy even more and support our 90nm production and 65nm development activities".

"Calibre has been adopted at 19 of the top 25 semiconductor companies because we continue to deliver the industry's best performance, capacity and yield enhancement", said Joseph Sawicki, general manager, design-to-silicon division, Mentor Graphics.

"These RET advancements, combined with the fact that we now offer a single flow from design-to-silicon, make Calibre the fastest, most accurate and complete physical verification and subwavelength manufacturing solution available".

The improvements announced today address the requirements of both current and next-generation resolution enhancement techniques.

All increase ease-of-use and help to streamline the application of RET process.

All of the enhancements described above are in limited production use at leading beta customers with general availability in the second quarter of 2003.

The Calibre product line starts at $85,000.

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