Infineon sorts out nanometre designs

Infineon Technologies has adopted the Mentor Calibre design-to-silicon platform, and the embedded deterministic test product, TestKompress, as key enablers for its nanometre IC design strategy.

Infineon Technologies has adopted the Mentor Calibre design-to-silicon platform, and the embedded deterministic test (EDT) product, TestKompress, as key enablers for its nanometre IC design strategy.

"Our collaboration with Infineon has been very rewarding", said Walden C Rhines, Mentor Graphics Chief Executive Officer and Chairman of the Board of Directors.

"It exemplifies all facets of true collaboration - mutual goals, clear communication and groundbreaking technical advancements.

Infineon's choice of Calibre and TestKompress underscores Mentor's leadership position in critical aspects of next generation IC design flows".

The TestKompress product uses the patented EDT technology to dramatically reduce the amount of test data required for today's complex ICs while preserving test quality, offering Infineon a significant reduction in test data volume with minimum impact to their designs.

As a pioneer in design-for-test (DFT) and manufacturing test, Infineon played an integral role in the validation of the EDT technology and the TestKompress product, and has now adopted it for production IC test to maintain the highest test quality and reduce test costs.

As each new process node enables increased design size and complexity, it is essential that the design-to-silicon platform provides performance, efficiency and accuracy improvements to keep cycle times for transferring a design into manufacturing within the project window.

The Calibre design-to-silicon platform has provided these consistent improvements enabling Infineon to meet the demanding schedule requirements for the 90 nanometre generation designs and smaller.

"Because of its best-in-class quality and performance we decided to adopt the Calibre design-to-silicon platform for physical verification and OPC in our 90nm design flow", said Andreas von Schwerin, Director, Design Automation and Technology, Infineon Technologies.

"Calibre has the most comprehensive roadmap for advanced resolution enhancement technologies in the industry providing a solid capability for Infineon to build upon for its advanced logic designs.

In addition, Infineon expects significant benefits from Calibre's unique ability to retain hierarchy throughout the design flow".

"The Calibre OPC products were able to meet Infineon's Memory Products demanding requirements for accuracy and throughput for 110 and 90 nanometre memory designs", said Volker Kiefer, Senior Director, CAD and Software Development, Infineon Technologies.

"Post-processing cycle times for highly customized DRAM layout have been reduced significantly for the 110nm technology from several days per layer to one day per layer with the integrated Calibre design-to-silicon platform".

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