Tower joins the Calibre fan club

Edited by the Electronicstalk editorial team Jun 25, 2003

Tower Semiconductor has selected Mentor's Calibre design-to-silicon platform as its internal manufacturing standard.

Tower Semiconductor has selected Mentor's Calibre design-to-silicon platform as its internal manufacturing standard.

The Calibre tool suite now in place at Tower includes design rule checking (Calibre DRC), layout versus schematic (Calibre LVS), parasitic extraction (Calibre xRC) and resolution enhancement technologies (Calibre OPCpro).

As part of its foundry services, Tower offers a high-density Flash process for embedded memory applications, CMOS image sensors (CIS) for video cellular phones, still cameras and other imaging applications, and analogue components with extremely low noise for use in mixed analogue/digital devices.

"We chose Calibre because it offers a single design-to-silicon platform that meets our requirements for performance, capacity and accuracy", stated Sergio Kusevitzky, Vice President of IP and design services at Tower Semiconductor.

"Using Calibre not only streamlines our internal processes, thereby improving time to market, but also ensures that our customers receive fully qualified and extensive rule file support, which gives them a distinct market advantage".

"In nanometre design, post-layout modifications are required.

If they're not done right, it can create serious yield issues", said Joseph Sawicki, General Manager of Mentor's design-to-silicon division.

"The Calibre design-to-silicon platform of tools handles post-layout modifications with the highest accuracy and performance, which ultimately leads to more profitable IC manufacturing and reduced cycle time".