New tool brings complex mixed-signal SoCs together

ICassemble is a new tool for top-down floorplanning, advanced interactive and automatic routing, and chip assembly capabilities within the Mentor Graphics IC Station full-custom layout environment.

ICassemble offers top-down floorplanning, advanced interactive and automatic routing, and chip assembly capabilities within the Mentor Graphics IC Station full-custom layout environment.

ICassemble is built into the IC Station tool - with a common database and integrated user interface - allowing SoC designers to plan, implement and connect blocks within a physical layout environment, eliminating the need for time-consuming and error-prone data abstractions and conversions.

By using ICassemble's automated and correct-by-construction capabilities in combination with the IC Station product's custom editing tools, designers can gain significant productivity benefits while achieving custom-quality layout for today's complex mixed-signal designs.

"We've been witnessing a dramatic increase in the complexity of our designs over the last few years", said Ludger Krucke, Vice President of the Design Department at Elmos Semiconductor, one of Europe's leading ASIC manufacturers.

"ICassemble has been a powerful and much-needed addition to our design flow, giving our designers the ability to significantly decrease the time required to stitch together analogue and digital blocks on our chips.

On one design, an automotive controller chip with hundreds of top-level nets, we successfully reduced the routing and assembly time by a factor of four".

Currently, the majority of mixed-signal chip planning is done by hand, a slow and laborious process that can lead to design errors and numerous iterations.

During final assembly, the completed blocks are also placed and routed manually without aid of design-rule-correct automation.

ICassemble is the only tool that addresses these problems with three powerful technologies, all integrated within a full custom layout environment: a schematic- and netlist-driven floorplanner, IRoute, an auto-interactive router, and ARoute, an automatic, gridless shape-based router.

All three components work off a unified set of design constraints that can be manipulated to control aspects such as pin placement, wiring, timing, shielding and signal integrity to achieve design-rule-correct layouts.

The ICassemble floorplanner facilitates top-down chip planning based on global connectivity and design constraints to speed design closure.

On establishing hierarchical connectivity from disparate sources such as schematics and/or netlists, designers can partition the chip, estimate block sizes, and then place the blocks and assign pin locations so as to minimise congestion and wire lengths of critical signals.

IRoute is an interactive router to speed up signal routing at any level of hierarchy.

In the early chip planning stage, IRoute can rapidly route power buses and critical signals to meet timing constraints.

At the block level, IRoute can automate point-to-point connections, buses and mirrored routes.

During engineering change orders (ECOs), IRoute can quickly fix changes by intelligently pushing and shoving circuitry out of the way to complete connections.

In all cases, IRoute's inherent adherence to constraints on shielding, spacing, widths, and directions of wires, along with its ability to look up and the down the hierarchy guarantees correct-by-construction results.

ARoute is an iterative rip-up and reroute tool that allows bulk routing of nets, selected by region or group, to rapidly complete chip assembly in a fraction of the time required for manual routing.

ARoute's N-layer and shape-based technology makes it suitable at all levels of hierarchy, from the device to the full chip.

Its layouts meet DRC rules since it is able to recognise and avoid blockages both in sub-blocks and at higher levels.

By placing appropriate constraints on wire spacing, widths, and shielding it can be driven to produce results that meet signal integrity requirements.

"The increase in analogue content on SoC designs is forcing more layout teams to merge digital and analogue blocks on a single chip", said Jue-Hsien Chern, Vice President and General Manager, Deep Submicron Division, Mentor Graphics.

"There is no other solution in the market today that provides ICassemble's top-down planning and routing capability integrated within a full-custom layout design tool".

The ICassemble tool is priced at $75,000 and is available today on Linux, Sun Solaris and HP-UX operating systems.

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