Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre xRC
Edited by the Electronicstalk Editorial
Team on 01 August 2003
Faraday uses xRC for parasitic
extraction
Faraday Technology is using the Mentor Graphics Calibre xRC product as its transistor level and GDSII-based gate level parasitic extraction tool for SoC designs.
Faraday Technology has selected the Mentor Graphics Calibre xRC product as its transistor level and GDSII-based gate level parasitic extraction tool for SoC designs Calibre xRC is part of the Calibre design-to-silicon solution
This article was originally published on Electronicstalk on 2 Sep 2002 at 8.00am (UK)
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Transistor-level parasitic extraction for SoCs
Calibre xRC is a full-chip, transistor-level parasitic extraction tool that addresses the performance and accuracy requirements of today's most complex analogue mixed-signal SoC designs.
Parasitic extraction validated for 90nm process
The Calibre xRC transistor-level parasitic extraction solution has been silicon validated by UMC for its 90nm process technology.
"We chose the Calibre xRC product based on our need for accuracy and performance at the parasitic extraction phase of the design flow", said Dr Jim Wang, Director of Design Development Division at Faraday.
"The Calibre xRC tool allows us to run both GDSII based gate- and transistor-level extraction with the same tool.
It also provides seamless upstream integration with the Calibre LVS tool to enable back-annotation of simulation results to the source schematic netlist.
Further reading
New engines improve nanometre parasitic extraction
New resistance and capacitance engines for Calibre xRC enable the industry's most accurate simulation of nanometre technology.
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
Its performance is 30 to 80 times faster than the previous version of the xCalibre tool on the parasitic extraction for our digital, analogue, large memory block IP and full chip design".
Analogue/mixed-signal SoC designs require a robust parasitic extraction tool that delivers accurate, mixed-level parasitic data for comprehensive and accurate analysis and simulation.
The Calibre xRC tool offers AMS SoC designers a single parasitic extraction solution that is independent of design style or flow.
For designers of analogue or small blocks, The Calibre xRC product offers high accuracy and tight integration with popular layout environments.
For designers of digital, large block or full-chip designs, the Calibre xRC tool offers performance driven by Calibre's hierarchical polygon processing engine.
With this single parasitic extraction tool, design teams can now eliminate the costly maintenance of supporting multiple extraction tools.
"Increased complexity in circuit design is driving the need for more advanced analysis, which in turn, is driving the need for more accurate, intelligent parasitic data", said Joe Sawicki, Vice President and General Manager for the Mentor Graphics Design-to-Silicon Division.
"The integration between the Calibre LVS tool and the Calibre xRC product provides our customers the capability to get accurate parasitics for device-level, gate-level, and fully hierarchical circuit simulation".
In nanometre design, the handoff between IC layout and manufacturing has changed.
In previous technologies, the handoff was a simple DRC/LVS check at tapeout.
Now it is a multistep process where the layout database is modified so the design can be manufactured.
This presents a host of challenges.
Issues arise concerning process effects, photolithography, data volumes and acceptable yield.
The integrated Calibre design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, design for manufacturability (DFM), mask data preparation (MDP) and resolution enhancement technologies (RET), meets the challenges of every facet of the design-to-silicon transition with efficiency and accuracy.
In a continuing tradition of delivering advanced technology, the Calibre design-to-silicon platform of integrated tools is recognized as the industry standard worldwide to address the complexities of advanced IC design.
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