Alliance to aid nanometre design

Mentor Graphics has joined the Chartered Semiconductor NanoAccess Alliance.

Mentor Graphics has joined the Chartered Semiconductor NanoAccess Alliance.

Mentor Graphics and Chartered are collaborating to provide extensive design support for 90nm SoC manufacturing technologies from Chartered, one of the world's top three dedicated semiconductor foundries.

The companies are jointly developing 90nm technology files and models for Calibre DRC, Calibre LVS and Calibre xRC that exploit the most advanced physical verification, parasitic extraction and resolution enhancement capabilities of the Calibre design-to-silicon platform, which is Chartered's "golden" internal standard for design rule checking (DRC).

"The Calibre design-to-silicon platform has a long track record of silicon success, and is well integrated with a wide variety of design creation environments", said Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered.

"Mentor's Calibre is already an important part of the leading-edge design ecosystem for many companies today, and our joint efforts ensure that they have access to the proven design and manufacturing technologies needed for first-pass silicon success at 90nm".

"We're expanding the Calibre design-to-silicon platform to answer the trends spurred by new design flows and manufacturing requirements at 90nm", said Joe Sawicki, Vice President and General Manager, Design-to-Silicon Division, Mentor Graphics.

"For example, the latest addition to the Calibre design-to-silicon platform, Calibre xRC, addresses the need for rapid, high-capacity, transistor-level parasitic extraction to enable more accurate post-layout analysis and ensure first-pass silicon success.

Our work with Chartered enables companies to apply these capabilities to their leading-edge designs with Chartered's 90nm process".

Mentor Graphics is an inaugural member of Chartered's NanoAccess Alliance, and joins the extensive system of industry-leading library, electronic design automation, intellectual property and outsourced design and manufacturing services companies.

The NanoAccess Alliance brings together critical SoC technologies and services with Chartered's NanoAccess semiconductor manufacturing processes for 90nm and beyond.

Chartered and the NanoAccess Alliance companies promote access to open design solutions that allow foundry customers more control over their leading-edge design and manufacturing options.

In nanometre design, the handoff between IC layout and manufacturing has changed.

In previous technologies, the handoff was a simple DRC/LVS check at tapeout.

Now it is a multistep process where the layout database is modified so the design can be manufactured.

This presents a host of challenges.

Issues arise concerning process effects, photolithography, data volumes and acceptable yield.

To meet these challenges, design teams rely on the integrated Calibre design-to-silicon platform, which includes physical verification, full-chip, transistor-level parasitic extraction, design for manufacturability (DFM), mask data preparation (MDP), optical proximity correction (OPC) and resolution enhancement technologies (RET).

The Calibre design-to-silicon platform of integrated tools is recognised as an industry-leading solution that addresses the complexities of advanced IC design.

Calibre DRC and Calibre LVS (layout versus schematic) technology files for Chartered's 90nm process are available now from Chartered.

Calibre xRC (parasitic extraction) files will be available in Q4 2003.

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