Product category:
Design and Development Hardware
News Release from: Mentor Graphics UK | Subject: PCI Express FPGA development system
Edited by the Electronicstalk Editorial
Team on 14 October 2003
FPGA platform speeds PCI Express
development
A new flexible development solution supports a variety of uses in the development, prototyping and verification of PCI Express-based systems in FPGAs.
A new flexible development solution supports a variety of uses in the development, prototyping and verification of PCI Express-based systems in FPGAs The system offers a fast track to designers looking for rapid time to market, and provides a means to achieve future compliance certification
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
Related stories
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
The flexible development solution supports endpoints, legacy endpoints, switches, advanced switches and root complexes, providing unprecedented capability for rapid prototyping, development and debugging that is the main reason for the explosive growth in FPGA-based systems.
The development solution can be configured with either Altera's Stratix GX EP1SGX25F or Stratix GX EP1SGX40G transceiver-based FPGAs.
It also includes flexible PCI Express signal routing via Infiniband cabling, test attachments, JTAG programming, passive cards and onboard DRAM.
Further reading
Mentor and Xilinx have cores for communications
Mentor Graphics and Xilinx have released two high-level IP products to accelerate the design cycle of high-density FPGAs in communications applications.
Mentor upgrades wiring harness design suite
Mentor Graphics has upgraded its Capital H wire harness engineering software, used primarily by the automotive and aerospace industries.
Board timing analysis tool upgraded
Mentor Graphics and Altera have jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis.
The development solution supports up to 20 lanes of traffic that can be allocated to different ports with suitably configured PCI Express intellectual property cores from Mentor Graphics.
It also supports varied links per port and multiport devices with the capability to adapt to either slot- or edge-based systems via inexpensive passive boards that communicate PCI Express through a compatible cable to the desired arrangement of PCI Express slots or edge connectors.
The development solution includes the physical layer, data link layer and transaction layer functionality, enabling the development of complete end point, switch and root complex solutions.
The core operates at 2.5Gbit/s link speed, using the multigigabit transceivers featured in Altera's Stratix GX devices that provide clock data recovery, 8B/10B encoding, 3.125Gbit/s serdes and Tx/Rx FIFOs.
"Providing complete, flexible PCI-Express development solutions is a crucial part of Altera's strategy to accelerate the design and development of high-bandwidth serial PCI Express solutions", said Justin Cowling, Director of Marketing for Altera's Intellectual Property Business Unit.
"This board gives customers immediate access to the latest high-speed serial I/O FPGA technology and provides users the fastest and easiest design path to PCI Express".
"This solution underpins our strong standards compliance-centric development methodology", said David Wood, Director of Product Marketing for the Intellectual Property division of Mentor Graphics.
"We firmly believe that customers must have confidence in IP through hardware verification and eventual compliance validation.
This development solution places Mentor Graphics in a strong position to be the leading provider of compliant PCI Express IP products".
It is also critically important to be able to verify designs using "real world" PCI Express traffic.
Adopters of PCI express always need to validate that their devices interface properly with the PCI Express standards under real conditions.
The development solution, in conjunction with Mentor Graphics IP and emulation technology provides customers an unprecedented ability to validate their systems, providing millions of cycles of throughput.
This puts Mentor Graphics at the leading edge of verifying complex PCI Express-based SoC designs.
The development solution shows a PCI to PCI Express configuration using Mentor PCI Express IP cores.
The IP is designed to be very flexible with a rich set of configurable features to allow the IP to be tuned for particular applications and bandwidths.
Configurable options include the number of virtual channels, the number of lanes (initially up to 16) and links per port and the maximum payload size.
Flow control is provided for different types of traffic, for instance allowing "cut-through" transfer of time critical data.
"It is fundamentally important that engineers have access to flexible development solutions to accelerate time to market for PCI Express-based systems", said Jim Pappas, Director of Initiative Marketing for Intel's Enterprise Platform Group.
"With broad availability of PCI Express solutions across Intel's desktop, mobile, server and communications platforms expected to initiate next year, availability of development solutions today will aid in keeping designers on track with product delivery".
The development solution will be available October 2003 and will be initially reserved for preferred customers of Altera FPGA and Mentor IP products.
• Mentor Graphics UK: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

