Verification accelerator supports System C

An updated version of the VStation TBX verification accelerator delivers full support for the leading system design languages.

An updated version of the VStation TBX verification accelerator delivers full support for the leading system design languages.

The VStationTBX tool now accelerates test benches in System C, generating verification results more than 500 times faster than cosimulation methods, and more than 10,000 times faster than software simulation.

The updated VStationTBX tool extends the Mentor Graphics Scalable Verification Platform, an interconnected suite of tools providing system-level verification and debugging for complex ASIC and SoC designs.

The VStationTBX tool, through its test bench compiler, compiles behavioural hardware description language (HDL) along with RTL, allowing designers to quickly map behavioural Verilog testbenches and memories into the VstationPro emulator.

This eliminates the performance bottlenecks and remodelling effort of cosimulation, allowing design teams to save months on testbench execution and creation.

In addition, the VStationTBX tool provides automated support for transaction-based modelling methods and standard verification languages such as SystemC, combining accelerated verification with the power of abstraction, and directed random testing.

By combining the test bench compilation and transaction-based verification capabilities in the VStationTBX tool, designers can incrementally improve the effectiveness, reusability and performance of their current testbenches, increasing design engineer efficiency and providing a scalable testbench methodology from software simulation to high-performance acceleration.

"The improvements we are making to the VStationTBX tool will allow customers to use hardware to speed complex system verification tests", said Eric Selosse, Vice President and General Manager of the Mentor Graphics Emulation Division.

"Our verification acceleration products have been a key component of more than 50 successful tapeouts so far and are facilitating the migration to the widespread use of transaction-based verification and directed random testing together with acceleration, helping customers to shorten their verification cycles and get quality products to market faster".

The VStationTBX (TestBench-XPress) tool is a verification accelerator for design and verification teams who are dissatisfied with the performance and productivity of their software simulations.

The VStationTBX tool is based on Mentor's unique TestBench Compiler and automated transaction technology, revolutionizing the quality of verification performance by providing access to minutes of real-time verification and high-level test benches.

Unlike traditional cosimulation, which is limited in performance, the VStationTBX tool compiles two-state behavioural Verilog, including behavioural memory models into the emulator, executing it directly.

The VStationTBX tool's TestBench Compiler provides an initial 20-200x performance increase for existing verification environments.

Once a customer is enjoying this initial performance boost, the VStationTBX tool enables them to incrementally migrate to higher abstraction, performance and productivity by using Mentor's third generation of transaction-based technology to smoothly connect abstract C or hardware verification language (HVL) models to their design and test bench components in the emulator.

The VStationTBX tool's combination of testbench compilation and high speed automated transaction interface results in performance of 1000 to 10,000 times simulation with high verification productivity and reuse.

The VStationTBX tool is the first tool to offer this incremental migration capability.

The VStationTBX tool was recent highlighted by MIPS Technologies in the verification of its 24K family of cores.

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