Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 17 May 2004
Simtek adopts parasitic extraction
solution
Simtek Corp has adopted Calibre xRC, Mentor's parasitic extraction solution for nanometre design, for its high-performance nonvolatile memory designs.
Calibre xRC, Mentor's parasitic extraction solution for nanometre design, has been adopted by Simtek Corp for its high-performance nonvolatile memory designs Calibre xRC was chosen for its ability to output optimised hierarchical parasitic data for signal and power net analysis, and for its integration with Nassda's post-layout hierarchical simulation tool, HSIM
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
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Calibre xRC is the first and only parasitic extraction tool to meet the stringent demands of nanometre technologies.
"Previous extraction tools flattened the data and made it impossible for us to simulate effects of parasitics in large designs", said David Still, Vice President of Engineering for Simtek.
"Calibre xRC quickly produced a compact hierarchical netlist that allowed us to validate and simulate our design using the hierarchical simulation tools in our design flow".
Calibre xRC offers transistor-level parasitic extraction for accurate modelling of nanometre designs.
It is integrated into many design and simulation flows, allowing designers to work in their native frameworks while providing the accuracy and performance required for complex nanometre analysis.
"Providing parasitic data hierarchically for back annotation to source netlists is a unique capability to Calibre xRC extraction".
"Calibre xRC DSPF data formats and extraction methods have been optimised for Nassda's preferred hierarchical simulation flow for both signal and power network analysis", said Graham Bell, Senior Director of Marketing, Nassda.
"With this flow, our mutual customers can realise high accuracy and enhanced performance during hierarchical extraction and simulation of large nanometre designs, and because of much greater capacity, be able to perform post-layout analysis that was previously impossible to achieve".
"Enabling hierarchical netlisting is one of the goals of our nanometre silicon modelling initiative", said Joe Sawicki, Vice President and General Manager of the Design-to-Silicon Division at Mentor Graphics.
"In collaborating with Nassda, we have developed a robust solution for Simtek's transistor-level extraction and simulation dilemma for large designs".
"The combination of Calibre xRC and the HSIM family of products gives designers a unique hierarchical approach for the analysis of post-layout effects for signal, and power net analysis".
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