Product category:
Design and Development Software
News Release from: Mentor Graphics UK | Subject: Calibre xRC
Edited by the Electronicstalk Editorial
Team on 30 June 2004
Parasitic extraction validated for 90nm
process
The Calibre xRC transistor-level parasitic extraction solution has been silicon validated by UMC for its 90nm process technology.
The Calibre xRC transistor-level parasitic extraction solution has been silicon validated by UMC for its 90nm process technology Calibre xRC is an advanced tool that meets the stringent demands of nanometer technologies
This article was originally published on Electronicstalk on 2 Sep 2002 at 8.00am (UK)
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Transistor-level parasitic extraction for SoCs
Calibre xRC is a full-chip, transistor-level parasitic extraction tool that addresses the performance and accuracy requirements of today's most complex analogue mixed-signal SoC designs.
Especially significant for 90nm designs is the pairing of Calibre with Calibre LVS, the layout versus schematic (LVS) tool.
This combination provides actual measured device parameters that can be back-annotated to the source netlist for post layout analysis.
This is a key factor in accurate nanometer silicon modelling, positively impacting yield and contributing toward first pass success of integrated circuit designs.
"At 90nm, it is imperative that our customers have access to the most advanced methods of achieving design and silicon success", said Ken Liou, Division Director, Design Support Division at UMC.
"Calibre's accuracy, capability and integration in physical verification and parasitic extraction will provide a proven solution that our customers can quickly adopt in their flows".
"UMC is ensuring the success of nanometre designs by directly addressing the physical issues that can hamper that success", said Joe Sawicki, Vice President of the Design-to-Silicon Division at Mentor Graphics.
"By validating tools engineered for advanced processes, customers will be prepared for the shrinking geometries of the future".
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