Product category:
Design and Development Software
News Release from: Mentor Graphics UK
Edited by the Electronicstalk Editorial
Team on 10 March 2005
Fraunhofer Institute adopts C synthesis
tool
The Fraunhofer Institute for Integrated Circuits IIS has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications.
The Fraunhofer Institute for Integrated Circuits IIS, a world-renown audio and video research laboratory located in Erlangen, Germany, has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications After an evaluation comparing leading high-level synthesis tools, Fraunhofer IIS chose the Catapult C Synthesis tool based on quality of results, time savings, ease of use, and the tool's compatibility with the company's C/C++ design flow
This article was originally published on Electronicstalk on 21 Feb 2001 at 8.00am (UK)
Related stories
Mentor Graphics and UMC deliver IC design kits
Mentor Graphics and UMC have joined to deliver a complete turnkey design flow, including the availability of IC design kits, for UMC's RF and analogue/mixed-signal process technologies.
Mentor supports TI DSPs and MCUs
Mentor Graphics is the first to reach agreement with Texas Instruments to deliver coverification processor support packages (PSPs) for Texas Instruments DSP and microcontroller solutions.
"During our evaluation, we found Catapult C's quality of results and ease of use to be very convincing".
"Using the tool, we expect a 5-10x improvement in productivity for algorithmic blocks, compared with HDL synthesis", said Frank Mayer, Design Manager, Fraunhofer IIS.
"The Catapult C tool's ability to use pure C code as input fits very well in our design flow, allowing us to automatically generate hardware directly from our untimed C/C++ system models regardless of the target technology".
Further reading
Mentor and Xilinx have cores for communications
Mentor Graphics and Xilinx have released two high-level IP products to accelerate the design cycle of high-density FPGAs in communications applications.
Mentor upgrades wiring harness design suite
Mentor Graphics has upgraded its Capital H wire harness engineering software, used primarily by the automotive and aerospace industries.
Board timing analysis tool upgraded
Mentor Graphics and Altera have jointly announced support for the STAMP timing file format, allowing PLD and PCB designers to easily share PLD timing data for efficient board-level timing analysis.
"Based on the success of our evaluation, we immediately deployed Catapult C in production design projects".
Fraunhofer IIS develops digital broadcast applications that depend on complex digital signal processing (DSP) algorithms.
The organisation typically implements the full system in field programmable gate arrays (FPGA) as a prototype for real-time performance validation before retargeting the design to an application specific integrated circuit (ASIC) for production.
Manual register-transfer level (RTL) creation for FPGA prototypes and ASICs were found to be too inefficient and error prone, and left no time for design space exploration.
This triggered the decision to explore high-level synthesis to reduce manual development time and validation effort.
For the past five years, Fraunhofer IIS has employed first-generation behavioural synthesis, using traditional HDL input, to shorten device development time.
Recently, the organisation decided to move beyond behavioural synthesis to explore algorithmic synthesis, which uses pure, untimed system models as input.
Algorithmic synthesis requires far less implementation effort, allowing designers to specify interfaces and hierarchy using constraints, and instantly target FPGA or ASIC implementations with the push of a button.
The Catapult C Synthesis tool is the only product to synthesise a C++ source where both the core algorithm and interface are untimed.
As a result, designers can perform detailed "what-if" analysis on varying micro-architecture and interface scenarios achieving fully optimised hardware designs.
The tool creates RTL that can be synthesised into gates using standard RTL synthesis products, enabling it to fit within a wide variety of tool flows.
"Fraunhofer IIS is an expert in using high-level synthesis to achieve time-to-market and quality goals for their communication and broadcasting systems", said Simon Bloch, General Manager of Mentor Graphics' Design Creation and Synthesis Division.
"We are honoured that such an outstanding organisation has selected Catapult C Synthesis as it deploys the benefits of algorithmic synthesis".
• Mentor Graphics UK: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
