Accellera accepts library donation

Edited by the Electronicstalk editorial team Apr 4, 2005

Mentor Graphics has donated its SystemVerilog Assertion version of the Open Verification Library to Accellera, the organisation for electronic design industry standards.

Mentor Graphics Corp has donated and received acceptance of its SystemVerilog Assertion (SVA) version of the Open Verification Library (OVL) to Accellera, the organisation for electronic design industry standards.

Mentor Graphics 0-In verification business unit developed the industry's first and most widely used assertion library for functional verification and is the leading supplier of assertion-based verification (ABV) tools.

The donated library is designed for use with multiple verification technologies including simulation, formal verification and emulation.

"Accellera is pleased to receive this SVA donation from Mentor Graphics".

"Mentor's strong commitment and leadership in standards, combined with their expertise in assertions, will be invaluable to the committee going forward", stated Bryan Bullis, Chairman of the OVL Committee of Accellera.

"This donation provides the foundation for a high quality, standards-based assertion library solution to improve the verification productivity of all design teams".

"The Accellera committee, combined with Mentor's commitment to work within the technical committees, will help accelerate the adoption of SystemVerilog and ABV".

The Accellera OVL Committee also approved the creation of a new subcommittee for the OVL-SVA library, to be chaired by Mentor.

This subcommittee will be responsible for delivering an Accellera standard library and maintain and enhance the OVL-SVA library over time.

"Assertion-based verification is rapidly becoming the standard verification methodology for many teams working on system-on-chip (SoC) and ASIC designs", said Robert Hum, Vice President and General Manager Mentor Graphics Design Verification and Test Division.

"With Mentor Graphics' strong commitment to industry standards, it was natural for us to kick-start the standardisation with a donation of an assertion library written with SystemVerilog Assertion that is consistent and compatible with the existing OVL".